Maxim-integrated 73S12xxF Software Bedienungsanleitung PDF herunterladen (Seite 4)

73S12xxF Software User Guide UG_12xxF_016

4 Rev. 1.50

4.5 Test Tools and Certification/compliance Tests ........................................................................ 85

4.5.1 EMV LEVEL I Certification Tests .............................................................................. 86

4.5.1.1 EMV Test Mode ..................................................................................... 86

4.5.1.2 MasterCard Loopback Test .................................................................... 87

4.5.1.3 VISA-1 Loopback Test ............................................................................ 90

4.5.2 VISA-2 Loopback Test .............................................................................................. 91

5 Related Documentation .............................................................................................................. 92

6 Contact Information .................................................................................................................... 92

Revision History .................................................................................................................................. 93

Figures

Figure 1: Software Architecture Diagram .................................................................................................. 9

Figure 2: Device Options for Building with the Boot Loader

.................................................................... 12

Figure 3: Target Options for Building with the Boot Loader

.................................................................... 13

Figure 4: C51 Options for Building with the Boot Loader

........................................................................ 13

Figure 5: Target Options for Building with the DFU Boot Loader

............................................................ 15

Figure 6: C51 Options for Building with the Boot Loader

........................................................................ 16

Figure 7: Memory Layout

....................................................................................................................... 19

Figure 8: Smart Card Rx/Tx Timing

........................................................................................................ 31

Figure 9: Boot Loader Scenario

............................................................................................................. 67

Figure 10: FLASH Download and Programming Process

....................................................................... 68

Figure 11: EMV PSE Test Flow Chart

.................................................................................................... 87

Figure 12: MCI Test Flow Chart with PTS/PPS

...................................................................................... 88

Figure 13: MCI Test Flow Chart without PTS/PPS

................................................................................. 89

Figure 14: VISA-1 Loopback Test Flow Chart

........................................................................................ 90

Figure 15: VISA-2 Loopback Test Flow Chart

........................................................................................ 91

Tables

Table 1: Upper 1 KB External Data Memory layout ................................................................................ 20

Table 2: IRAM Special Function Register Map

....................................................................................... 20

Table 3: Interrupt Sources and Priority Level

.......................................................................................... 21

Table 4: Clock Speeds and Baud Rates Supported

............................................................................... 51

Table 5: Security Mode Actions Allowed

................................................................................................ 70

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