Maxim-integrated 78M6610+PSU Hardware Design Guidelines Bedienungsanleitung Seite 1

78M6610+PSU Hardware Design Guidelines APPLICATION NOTE AN_6610_107 July 2012 Rev 0 1 1 Introduction This application note describes hardware

78M6610+PSU Hardware Design Guidelines AN_6610_107 10 Rev 0 GNDDV3P3AV3P3DGNDA1000pF22µF (BULK)V3P3Place Capacitors Close to V3P3A0.1µFCAPACITOR’

AN_6610_107 78M6610+PSU Hardware Design Guidelines Rev. 0 11 4.2 Clock Circuitry The 78M6610+PSU can utilize an external 20.000 MHz crystal for

78M6610+PSU Hardware Design Guidelines AN_6610_107 12 Rev 0 4.3 Reset Circuitry The 78M6610+PSU employs an active low Reset input pin. Figure 8

AN_6610_107 78M6610+PSU Hardware Design Guidelines Rev. 0 13 4.4 Connecting 5 V Devices All digital input pins (DIO pins) of the 78M6610+PSU are

78M6610+PSU Hardware Design Guidelines AN_6610_107 14 Rev 0 5 Printed Circuit Board Layout Guidelines The 78M6610+PSU minimizes the external com

AN_6610_107 78M6610+PSU Hardware Design Guidelines Rev. 0 15 5.2 Crystal Oscillator Components The 78M6610+PSU Evaluation Board has the crystal

78M6610+PSU Hardware Design Guidelines AN_6610_107 16 Rev 0 5.3 LINE Voltage Resistor Network The LINE voltage resistor network can be split bet

AN_6610_107 78M6610+PSU Hardware Design Guidelines Rev. 0 17 5.4 Shunt Current Sensor The current shunt network can also be split between the 78

78M6610+PSU Hardware Design Guidelines AN_6610_107 18 Rev 0 5.6 V3P3 Decoupling Capacitors Place the V3P3 decoupling capacitors close to the 3.3

AN_6610_107 78M6610+PSU Hardware Design Guidelines Rev. 0 19 6 Revision History Revision Date Description 0 7/27/2012 First publication.

78M6610+PSU Hardware Design Guidelines AN_6610_107 2 Rev 0 2 Recommended Configuration Resistive current shunts and voltage dividers are commonl

AN_6610_107 78M6610+PSU Hardware Design Guidelines Rev. 0 3 2.1 Sensor Connections The basic connections for a shunt-based system are represent

78M6610+PSU Hardware Design Guidelines AN_6610_107 4 Rev 0 2.1.1 Line Voltage Resistor Divider Selection The input AC line voltage is scaled dow

AN_6610_107 78M6610+PSU Hardware Design Guidelines Rev. 0 5 2.1.2 Shunt Resistor Selection The value of the shunt to be used is a tradeoff betw

78M6610+PSU Hardware Design Guidelines AN_6610_107 6 Rev 0 2.2 Safety Precautions With V3P3 directly connected to NEUTRAL, the 78M6610+PSU’s Gro

AN_6610_107 78M6610+PSU Hardware Design Guidelines Rev. 0 7 3 Alternate Configuration Voltage and current sensors can alternatively be located r

78M6610+PSU Hardware Design Guidelines AN_6610_107 8 Rev 0 3.1 Current Transformer Selection The consideration for selecting a current transform

AN_6610_107 78M6610+PSU Hardware Design Guidelines Rev. 0 9 4 Device Configuration The following section covers the rest of the hardware interfa