Maxim-integrated 78Q8430 Software Driver Bedienungsanleitung

78Q8430 Software Driver Development Guidelines February, 2008 Rev. 1.0

78Q8430 Software Driver Development Guidelines UG_8430_004 Disabling Hardware Jabber Protection Use the following procedure to disable hardware jabbe

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 11 triggers an under-run interrupt for QUE 2 if the previous frame has not be

78Q8430 Software Driver Development Guidelines UG_8430_004 STEP 1: Enable multicast filter #1 in the CAM. Modify CAM rule 0x7D (multicast filter #1

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 13 The following procedure is used to set the HNR Timer duration: STEP 1:

78Q8430 Software Driver Development Guidelines UG_8430_004 The host drop feature must never be used to drop a frame that is 4 bytes or less in size.

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 15 3.9 Add Padding The transmit circuit has the ability to add padding to tra

78Q8430 Software Driver Development Guidelines UG_8430_004 4 Packet Classification The 78Q8430 packet classification engine consists of a content add

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 17 Table 2: Wildcard Address Example Byte [5] Byte [4] Byte [3] Byte [2]

78Q8430 Software Driver Development Guidelines UG_8430_004 Reg. Field Value to write CAR ADDR 0x70+N Data Match Value of MAC address byte [0] Dat

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 19 STEP 4: Enable the filter. Enable the unicast address filter N by modifyi

78Q8430 Software Driver Development Guidelines UG_8430_004 © 2008 Teridian Semiconductor Corporation. All r

78Q8430 Software Driver Development Guidelines UG_8430_004 STEP 2: Write address and mask byte [1] through byte [4] to the CAM. For each byte, write

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 21 4.2.6 Negative Address Filters Any address filter, either multicast or un

78Q8430 Software Driver Development Guidelines UG_8430_004 STEP 2: Write pattern and mask byte [1] through byte [4] to the CAM. For each byte, CAM r

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 23 4.4.1 Enable Magic Packet Use the following procedure to enable the Magic

78Q8430 Software Driver Development Guidelines UG_8430_004 4.5 Classification Interrupts The classification engine has an interrupt feature. The

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 25 5 Media Controller Offload Features The 78Q8430 has several features that

78Q8430 Software Driver Development Guidelines UG_8430_004 STEP 2: Write the desired amount of data. Once the slave DMA Write Mode is set, all write

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 27 STEP 7: Read all available new data from QUE 0. The amount of new data in

78Q8430 Software Driver Development Guidelines UG_8430_004 STEP 13: Read the transmit status from TPSR. Reading the TPSR reads status words from the

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 29 STEP 3: Set the value of the PAUSE field in the WMVR value. This can be d

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 3 Table of Contents 1 Introduction ...

78Q8430 Software Driver Development Guidelines UG_8430_004 STEP 5: Check transmit QUE size for excessive use. The only appropriate response to a ful

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 31 STEP 5: Use SNOOP access to retrieve the hardware and protocol source add

78Q8430 Software Driver Development Guidelines UG_8430_004 Table 6: ICMP Frame Contents MAC Header IP Header . . . Dest. Addr. Src. Addr. Len/Type1V

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 33 Data Mask 0xFF Previous Hit Match 0x7B Previous Hit Mask 0x7F Byte Offs

78Q8430 Software Driver Development Guidelines UG_8430_004 STEP 4: Use SNOOP access to retrieve the IP destination address. The two MSBs of SNOOP

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 35 in the standard way and the BLOCK will still be available for a transfer o

78Q8430 Software Driver Development Guidelines UG_8430_004 5.7 Transmit Priority The standard transmit procedure uses transmit QUE 4. Frames can als

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 37 6 Counter Rollover Monitor (RMON) The 78Q8430 includes a block of hardwar

78Q8430 Software Driver Development Guidelines UG_8430_004 STEP 4: Read RRIR. A single bit will be set in RRIR for each receive counter that has rol

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 39 7 PHY Procedures This section describes the following procedures related t

78Q8430 Software Driver Development Guidelines UG_8430_004 5.4 Transfer Frame ...

78Q8430 Software Driver Development Guidelines UG_8430_004 Table 7: Auto-negotiation Registers Default Values Register Field / Function Default Val

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 41 STEP 1: Use procedure 7.2 to read the value of the MR0 register. STEP 2:

78Q8430 Software Driver Development Guidelines UG_8430_004 7.8 PHY Link Status Change The behavior of the MAC in half duplex mode is not the same as

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 43 8 EEPROM Operations The 78Q8430 provides logic for reading and writing an

78Q8430 Software Driver Development Guidelines UG_8430_004 9 Power Management 9.1 Sleep Procedure Use the following procedure to setup the sleep stat

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 45 10 BIST Use the following procedure to run the built in self-check for the

78Q8430 Software Driver Development Guidelines UG_8430_004 11 Software Reset Use the following procedure to reset the QUEs and the MAC: STEP 1: Set

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 47 12 Related Documentation The following 78Q8430 documents are available fro

78Q8430 Software Driver Development Guidelines UG_8430_004 Appendix A – Default CAM Rule Summary Table 9: Default CAM Rules Rule# Previous Hit Match

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 49 Rule# Previous Hit Match Previous Hit Mask Data Match Data Mask Match Con

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 5 1 Introduction The 78Q8430 is a 10/100 Fast Ethernet MAC and PHY controller

78Q8430 Software Driver Development Guidelines UG_8430_004 Rule# Previous Hit Match Previous Hit Mask Data Match Data Mask Match Control Byte Offs

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 51 Rule# Previous Hit Match Previous Hit Mask Data Match Data Mask Match Con

78Q8430 Software Driver Development Guidelines UG_8430_004 Appendix B – Acronyms Miscellaneous Acronyms ARC Address Resolution Controller CAM Con

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 53 Register Set Register Acronym Description CTL RCR Rule Control Register

78Q8430 Software Driver Development Guidelines UG_8430_004 Revision History Revision Date Description 1.0 2/13/2008 First publication. 54 Rev. 1.

78Q8430 Software Driver Development Guidelines UG_8430_004 2 List of Features Table 1 lists the 78Q8430 hardware supported features described in thi

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 7 Feature Description PageIP Firewall IP address filtering. 35IP Checksum

78Q8430 Software Driver Development Guidelines UG_8430_004 3 MAC Operations This section describes the procedures to implement the following 78Q8430

UG_8430_004 78Q8430 Software Driver Development Guidelines Rev. 1.0 9 3.2 Basic Receive The basic receive operation is achieved using the QUE0 re