Maxim-integrated DS5001FP Bedienungsanleitung

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1 of 26 052302
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, click here: http://www.maxim-ic.com/errata.
FEATURES
§ 8051-compatible microprocessor adapts to its
task
Accesses up to 128kB of nonvolatile
SRAM
In-system programming through on-chip
serial port
Can modify its own program or data
memory
Accesses memory on a separate byte-wide
bus
Performs CRC-16 check of NV RAM
memory
Decodes memory and peripheral chip
enables
§ High-reliability operation
Maintains all nonvolatile resources for
over 10 years
Power-fail reset
Early warning power-fail interrupt
Watchdog timer
Lithium backs user SRAM for
program/data storage
Precision bandgap reference for power
monitor
§ Fully 8051-compatible
128kB scratchpad RAM
Two timer/counters
On-chip serial port
32 parallel I/O port pins
§ Software security available with DS5002FP
secure microprocessor
PIN ASSIGNMENT (Top View)
P0.4AD4
CE2
PE2
BA9
P0.3/AD3
BA8
P0.2/AD2
BA13
P0.1/AD1
R/W
P0.0/AD0
VCC0
VCC
MSEL
P1.0
BA14
P1.1
BA12
P1.2
BA7
P1.3
PE3
PE4
BA6
P2.6/A14
CE3
CE4
BD3
P2.5/A13
BD2
P2.4/A12
BD1
P2.3/A11
BD0
VLI
BA15
GND
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P3.5/TI
PF
VRST
P3.4/T0
DS5001FP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P1.4
BA5
P1.5
BA4
P1.6
BA3
P1.7
PROG
BA2
RST
BA1
P3.0/RXD
BA0
P3.1/TXD
P3.2/INT0
P3.3/INT1
BA11
P0.5/AD5
PE1
P0.6/AD6
BA10
P0.7/AD7
CE1
NC
CE1N
BD7
A
LE
BD6
PSEN
BD5
P2.7/A15
BD4
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
DS5001FP
128k Soft Microprocessor Chip
www.maxim-ic.com
80-Pin MQFP
44-Pin MQFP
Seitenansicht 0
1 2 3 4 5 6 ... 25 26

Inhaltsverzeichnis

Seite 1 - 128k Soft Microprocessor Chip

1 of 26 052302Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiplerevisions of any d

Seite 2 - ORDERING INFORMATION

DS5001FP10 of 26Figure 6. DS5001FP CONNECTION TO 64k x 8 SRAMPOWER MANAGEMENTThe DS5001FP monitors VCC to provide power-fail reset, early warning powe

Seite 3 - Figure 1. BLOCK DIAGRAM

DS5001FP11 of 26ABSOLUTE MAXIMUM RATINGS*Voltage Range on Any Pin Relative to Ground -0.3V to (VCC + 0.5V)Voltage Range on VCC Related to Ground -0.3

Seite 4 - PIN DESCRIPTION

DS5001FP12 of 26DC CHARACTERISTICS (continued) (TA = 0°C to +70°C; VCC = 5V ±10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESInput Leakage Cur

Seite 5

DS5001FP13 of 26AC CHARACTERISTICSEXPANDED BUS MODE TIMING SPECIFICATIONS (TA

Seite 6 - MEMORY ORGANIZATION

DS5001FP14 of 26EXPANDED PROGRAM-MEMORY READ CYCLEEXPANDED DATA-MEMORY READ CYCLE

Seite 7

DS5001FP15 of 26EXPANDED DATA-MEMORY WRITE CYCLE

Seite 8

DS5001FP16 of 26AC CHARACTERISTICS (continued)EXTERNAL CLOCK DRIVE (TA = 0°C to +70°C; VCC = 5V ±10%)# PARAMETER SYMBOL MIN

Seite 9

DS5001FP17 of 26AC CHARACTERISTICS (continued)POWER CYCLE TIME (TA = 0°C to +70°C; VCC = 5V ±10%)# PARAMETER SYMBOL

Seite 10 - POWER MANAGEMENT

DS5001FP18 of 26AC CHARACTERISTICS (continued)SERIAL PORT TIMING, MODE 0 (TA = 0°C to +70°C; VCC = 5V ±10%)# PARAMETER SYMBOL MIN MAX

Seite 11 - = 5V ±10%)

DS5001FP19 of 26AC CHARACTERISTICS (continued)BYTE-WIDE ADDRESS/DATA BUS TIMING

Seite 12

DS5001FP2 of 26DESCRIPTIONThe DS5001FP 128k soft microprocessor chip is an 8051-compatible microprocessor based on NV RAMtechnology and designed for s

Seite 13 - AC CHARACTERISTICS

DS5001FP20 of 26BYTE-WIDE BUS TIMINGRPC AC CHARACTERISTICS, DBB READ (TA = 0°C to +70°C; VCC = 5V ±10%)# PARAMETER SYMBOL MIN MAX UNITS54CS , A0 Set

Seite 14 - 14 of 26

DS5001FP21 of 26RPC AC CHARACTERISTICS, DBB WRITE (TA = 0°C to +70°C; VCC = 5V ±10%)# PARAMETER SYMBOL MIN MAX UNITS60CS , A0 Setup to WRtAW0ns61ACS

Seite 15 - 15 of 26

DS5001FP22 of 26RPC TIMING MODE

Seite 16 - EXTERNAL CLOCK TIMING

DS5001FP23 of 26NOTES:All parameters apply to both commercial and industrial temperature operation unless otherwise noted.1) All voltages are referen

Seite 17 - POWER CYCLE TIMING

DS5001FP24 of 2680-PIN MQFPMMDIMMIN MAXA -3.40A1 0.25 -A2 2.55 2.87B 0.30 0.50C 0.13 0.23D 23.70 24.10D1 19.90 20.10E 17.70 18.10E1 13.90 14.10e 0.80

Seite 18 - SERIAL PORT TIMING, MODE 0

DS5001FP25 of 2644-PIN MQFP

Seite 19

DS5001FP26 of 26REVISION HISTORYThe following represent the key differences between 112795 and 073096 version of the DS5001FP datasheet. Please review

Seite 20 - BYTE-WIDE BUS TIMING

DS5001FP3 of 26Figure 1. BLOCK DIAGRAM

Seite 21 - PROG (T

DS5001FP4 of 26PIN DESCRIPTION80-PINMQFP44-PINMQFPSIGNAL DESCRIPTION11, 9, 7,5, 1, 79,77, 7531(P0.5)P0.0–P0.7General-Purpose I/O Port 0. This port is

Seite 22 - RPC TIMING MODE

DS5001FP5 of 2633, 35,379 and A15 respectively.71, 69,67, 65,61, 59,57, 5528, 26,24, 23,21, 20,19, 18BD7–0Byte-Wide Data-Bus Bits 7–0. This 8-bit, bid

Seite 23 - 23 of 26

DS5001FP6 of 26INSTRUCTION SETThe DS5001FP executes an instruction set that is object code-compatible with the industry standard 8051microcontroller.

Seite 24 - 80-PIN MQFP

DS5001FP7 of 26Figure 3. MEMORY MAP IN PARTITIONABLE MODE (PM = 0)Note: Partitionable mode is not supported when MSEL pin = 0 (128kB mode).

Seite 25 - 44-PIN MQFP

DS5001FP8 of 26Figure 4. MEMORY MAP WITH PES = 1

Seite 26 - REVISION HISTORY

DS5001FP9 of 26Figure 5 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in thisconfiguration, both program and data

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