Maxim-integrated DS4830A Optical Microcontroller Bedienungsanleitung PDF herunterladen (Seite 112)

DS4830A User’s Guide

112

controls whether the active or inactive clock edge is used to latch the data. When CKPHA is set to 1, data is sampled

on the inactive clock edge (clock returning to the idle state). When CKPHA is set to 0, data is sampled on the active

clock edge (clock transition to the active state). Together, the CKPOL and CKPHA bits allow four possible SPI data

transfer formats illustrated in Figure 12-2 and Figure 12-3. The Slave Select signal can remain asserted between

successive transfers. Table 12-1 illustrates the SPI modes.

Table 12-1: SPI Modes

CKPOL

CKPHA

MODE

SAMPLE POINT

Mode 0

Rising edge

Mode 1

Falling edge

Mode 2

Falling edge

Mode 3

Rising edge

CKPOL=0

CKPHA=1

CKPOL=1

CKPHA=1

MOSI/MISO

SSEL

SAS=1

Sampling Points

Transfer Cycle

LSBMSB

1 2 3 4 5 6 7 8

Figure 12-2

: SPI Transfer Formats (CKPHA=1)

CKPOL=0

CKPHA=0

CKPOL=1

CKPHA=0

MOSI/MISO

SSEL

SAS=1

Sampling Points

Transfer Cycle

LSB

MSB

1 2 3 4 5

6 7 8

MSB

MSB of

Transfer

Figure 12-3

: SPI Transfer Formats (CKPHA=0)

1 2 ... 107 108 109 110 111 112 113 114 115 116 117 ... 239 240

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