Maxim-integrated DS4830A Optical Microcontroller Bedienungsanleitung Seite 117
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DS4830A User’s Guide
117
12.4.3.2 – SPI Configuration Register (SPICF_M)
Bit
7
6
5
4
3
2
1
0
Name
ESPII
SAS
-
-
-
CHR
CKPHA
CKPOL
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
r
r
r
rw
rw
rw
BIT
NAME
DESCRIPTION
7
ESPII
SPI Interrupt Enable. Setting this bit to ‘1’ enables the SPI interrupt when MODF,
WCOL, ROVR or SPIC flags are set. Clearing this bit to ‘0’ disables the SPI interrupt.
6
SAS
Slave Active Select.
In Master mode, this is used only when mode fault is enabled.
If SAS = 0, then mode fault is detected when active low is detected on MSPICS pin.
If SAS = 1, then mode fault is detected when active high is detected on MSPICS pin.
5:3
Reserved
Reserved, Read Returns 0.
2
CHR
Character Length Bit. The CHR bit determines the character length for an SPI
transfer cycle. A character can consist of 8 or 16 bits in length. When CHR bit is ‘0’, the
character is 8 bits; when CHR is set to ‘1’, the character is 16 bits.
1
CKPHA
SPI Clock Phase Select. This bit is used with the CKPOL bit to determine the SPI
transfer format. When the CKPHA is set to ‘1’, the SPI will sample input data at an
inactive edge. When the CKPOL is cleared to 0, the SPI will sample input at an active
edge.
0
CKPOL
SPI Clock Polarity Select. This bit is used with the CKPHA bit to determine the SPI
transfer format. When the CKPOL is set to ‘1’
, the SPI uses the clock falling edge
as an active edge. When the CKPOL is cleared to 0, the SPI selects the clock rising
edge as an active edge.
12.4.3.3 – SPI Clock Register (SPICK_M)
Bit
7
6
5
4
3
2
1
0
Name
SPICK_M[7:0]
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
7:0
SPICK_M[7:0]
Clock Divide Ratio Bits. These bits select one of the 256 divide ratios (0 to 255) used for
the baud rate generator, with bit 7 as the most significant. The frequency of SPI baud rate
is calculated using the following equation:
SPI Baud Rate = ½ x Core Clock / (SPICK[7:0] + 1)
12.4.3.4 – SPI Data Buffer Register (SPIB_M)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
SPIB_M[15:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access*
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
*Unrestricted read, write is allowed outside of a transfer cycle; when the STBY bit is set, write is blocked and will
cause write collision error.
BIT
NAME
DESCRIPTION
15:0
SPIB_M[15:0]
SPI Data Buffer Bits. Data for SPI is read from or written to this location. The serial
transmit and receive buffers are separate but both are addressed at this location.
- DS4830A 1
- Optical Microcontroller 1
- User’s Guide 1
- Contents 2
- DS4830A User’s Guide 10
- SECTION 1 – OVERVIEW 11
- SECTION 2 – ARCHITECTURE 13
- 2.2 – Register Space 14
- 2.3 – Memory Types 15
- 2.5 – Data Alignment 22
- 2.6 – Reset Conditions 22
- 2.7 – Clock Generation 24
- INT_TRIG1 38
- INT_ALIGN 38
- BOOT_DIS 38
- SECTION 5 – INTERRUPTS 40
- 5.1 – Servicing Interrupts 41
- 6.1 – Detailed Description 45
- 6.3 – DAC Code Examples 47
- 7.1 – Detailed Description 48
- 7.3 – ADC Code Examples 63
- SECTION 8 – SAMPLE AND HOLD 65
- INT_TRIG_EN1 72
- INT_TRIG_EN0 72
- 9.1 – Detailed Description 73
- SECTION 10 – I 81
- 10.2 – I 90
- SECTION 11 – I 94
- C-COMPATIBLE SLAVE INTERFACE 94
- 11.1 – Detailed Description 95
- Detect START 96
- I2CSRI=1 96
- I2CBUS=1 96
- I2CBUSY=1 96
- 100 100
- 101 101
- 102 102
- 104 104
- 105 105
- 106 106
- 107 107
- 108 108
- 109 109
- 110 110
- SPI Slave 111
- 112 112
- 113 113
- 12.2 – SPI System Errors 113
- 114 114
- 115 115
- 116 116
- 117 117
- 118 118
- 119 119
- 120 120
- SECTION 13 – 3-WIRE 121
- 122 122
- 123 123
- Using PWMCN and 124
- 125 125
- 128 128
- 129 129
- 130 130
- 131 131
- 132 132
- 133 133
- 134 134
- FrequencyClockPWM 135
- FrequencyFrame 135
- 136 136
- 137 137
- 138 138
- 15.1 – Overview 138
- 140 140
- 141 141
- 142 142
- 143 143
- 16.1 – Detailed Description 143
- 144 144
- 145 145
- 146 146
- 147 147
- MULTIPLIER 148
- 149 149
- 150 150
- 151 151
- 152 152
- 153 153
- 154 154
- 155 155
- 156 156
- 19.1 - Overview 156
- 157 157
- 158 158
- 159 159
- 160 160
- 20.1 – TAP Controller 160
- 161 161
- 20.2 – TAP State Control 161
- 162 162
- 20.3 – Communication via TAP 162
- 163 163
- 164 164
- 165 165
- 166 166
- 167 167
- 168 168
- 169 169
- 170 170
- 21.2 – Debug Mode 170
- 171 171
- 172 172
- 173 173
- 174 174
- 175 175
- 176 176
- 177 177
- 178 178
- 179 179
- 22.1 – Detailed Description 179
- 180 180
- 181 181
- 182 182
- 22.2 – Bootloader Operation 182
- 183 183
- 184 184
- 22.3 – Bootloader Commands 184
- 185 185
- 186 186
- 187 187
- 188 188
- 189 189
- SECTION 23 – PROGRAMMING 190
- 191 191
- 192 192
- 193 193
- 194 194
- 195 195
- 196 196
- 197 197
- – Controlling Program Flow 197
- 198 198
- 199 199
- – Handling Interrupts 199
- 200 200
- – Accessing the Stack 200
- 201 201
- – Accessing Data Memory 201
- 202 202
- SECTION 24 – INSTRUCTION SET 203
- 204 204
- 205 205
- 206 206
- 207 207
- 208 208
- 209 209
- 210 210
- 211 211
- 212 212
- 213 213
- 214 214
- 215 215
- 216 216
- 217 217
- 218 218
- 219 219
- 220 220
- 221 221
- 222 222
- 223 223
- 224 224
- 225 225
- 226 226
- 227 227
- 228 228
- 229 229
- 230 230
- SECTION 25 – UTILITY ROM 231
- 232 232
- 233 233
- 234 234
- 235 235
- 236 236
- 237 237
- 25.4 Special Functions 237
- 238 238
- 25.5 – Utility ROM Examples 238
- SECTION 26 – MISCELLANEOUS 239
- 240 240
- 26.5 – Device Number and I 240
- C Bootloader Address Disable 240
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