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Maxim Integrated 4-4

MAX31782 User’s Guide

Revision 0; 8/11

Table 4-2. Peripheral Register Bit Functions (continued)

MODULE 4

PWMC2 00h PWMC2[15:0]

PWMR2 01h PWMR2[15:0]

PWMC3 02h PWMC3[15:0]

PWMR3 03h PWMR3[15:0]

TACHR2 05h TACHR2[15:0]

TACHR3 07h TACHR3[15:0]

PWMV2 08h PWMV2[15:0]

PWMCN2 09h — — — PWMCS PWMCR PWMPS[2:0] TFB — — DCEN — PWMEN ETB —

PWMV3 0Ah PWMV3[15:0]

PWMCN3 0Bh — — — PWMCS PWMCR PWMPS[2:0] TFB — — DCEN — PWMEN ETB —

TACHV2 0Ch TACHV2[15:0]

TACHCN2 0Dh — TRPS[1:0] — — TPS[2:0] TF TEXF — — TEXEN TACHE TACHIE —

TACHV3 0Eh TACHV3[15:0]

TACHCN3 0Fh — TRPS[1:0] — — TPS[2:0] TF TEXF — — TEXEN TACHE TACHIE —

MIIR4 10h — — — — —

— — — — — — — — —

TACH3 TACH2

MODULE 5

MCNT 00h OF MCW CLD SQU OPCS MSUB MMAC SUS

MA 01h MA[15:0]

MB 02h MB[15:0]

MC2 03h MC2[15:0]

MC1 04h MC1[15:0]

MC0 05h MC0[15:0]

MC1R 06h MC1R[15:0]

MC0R 07h MC0R[15:0]

PWMV4 08h PWMV4[15:0]

PWMCN4 09h — — — PWMCS PWMCR PWMPS[2:0] TFB — — DCEN — PWMEN ETB —

PWMC4 0Ah PWMC4[15:0]

PWMR4 0Bh PWMR4[15:0]

TACHV4 0Ch TACHV4[15:0]

TACHCN4 0Dh — TRPS[1:0] — — TPS[2:0] TF TEXF — — TEXEN TACHE TACHIE —

TACHR4 0Fh TACHR4[15:0]

TACHR5 11h TACHR5[15:0]

TACHV5 12h TACHV5[15:0]

TACHCN5 13h — TRPS[1:0] — — TPS[2:0] TF TEXF — — TEXEN TACHE TACHIE —

PWMC5 14h PWMC5[15:0]

PWMR5 15h PWMR5[15:0]

PWMV5 16h PWMV5[15:0]

PWMCN5 17h

— — —

PWMCS PWMCR PWMPS[2:0] TFB — — DCEN — PWMEN ETB —

MIIR5 18h

— — — — — — — — — — —

— — —

TACH5 TACH4

1 2 ... 30 31 32 33 34 35 36 37 38 39 40 ... 222 223

MAX31782 User’s Guide 1

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