
Maxim Integrated 6-3
MAX31782 User’s Guide
Revision 0; 8/11
6.1.2 Conversion Sequencing
The MAX31782 ADC performs a user-defined sequence of up to eight conversions. Each conversion in a sequence
is set up using one of the eight ADC configuration registers. The configuration registers are accessed by writing to
the ADDATA register when ADST.ADCFG = 1. The configuration register pointed to by ADDATA is selected using the
ADIDX bits in the ADST register. The individual configuration registers allows each of the conversions in a sequence to
select from the following options. For more information, see the 6.2.4 ADC Data and Configuration Register (ADDATA)
description.
• External temperature or voltage conversion
• Full-scale range
• Extended acquisition enable
• ADC conversion data alignment (left or right)
• Differential or single-ended conversion
• ADC channel selection
A sequence is set up in the ADADDR register by defining the starting conversion configuration address (ADSTART) and
an ending conversion configuration address (ADEND). The configuration start address designates the configuration
register to be used for the first conversion in a sequence. The configuration end address designates the configuration
register used for the last conversion in a sequence. A single channel conversion can be viewed as a special case for
sequence conversion, where the starting and ending configuration address is the same. The configuration registers
can be viewed as a circular register array where ADSTART does not have to be less than ADEND. For example, if
ADSTART = 1 and ADEND = 5, the sequence of conversions would be configurations 1, 2, 3, 4, 5. If ADSTART = 5 and
ADEND = 1, the sequence of conversions would be configurations 5, 6, 7, 0, 1.
The ADC has two conversion sequence modes, single and continuous, which is set by the ADCONT bit. The start
conversion bit (ADCONV) is used to start all conversions. In single sequence mode (ADCONT = 0), ADCONV remains
set until the ADC has finished conversion on the last channel in the sequence. In continuous mode (ADCONT = 1), the
ADCONV bit remains set until the continuous mode is stopped. Writing a 0 to the ADCONV bit stops the ADC operation
at the completion of the current ADC conversion. Writing a 1 to the ADCONV bit when ADCONV bit is already set to 1
is ignored by the ADC controller.
6.1.3 ADC Conversion Time
The ADC clock is derived from the system clock with divide ratio defined by ADC clock divider bits (ADCN.
ADCCLK[2:0]). Each sample takes 17 ADC clock cycles to complete. Three of the 17 ADC clock cycles are used for
sample acquisition, and the remaining 14 clocks are used for data conversion. The ADC automatically reads each mea-
surement twice and outputs the average of the two readings. This makes the resulting time for one complete conversion
34 ADC clock cycles.
Knowing this, it is possible to calculate the fastest ADC sample rate. The fastest ADC clock is:
ADC Clock = Sysclk/16 = 4MHz/16 = 250kHz
One conversion requires 34 ADC clocks:
Sample Rate = ADC Clock/34 Clocks = 250kHz/34 = 7.353ksps, or 136Fs per sample
The ADC has an internal power management system that automatically shuts down the ADC when conversions are
complete by clearing ADCONV to 0. After being shut down, the ADC begins conversions again when the ADCONV bit
is set to 1 again. After ADCONV is set to 1, the ADC requires 20 ADCCLK cycles to set up and power-up prior to begin-
ning the first conversion of the sequence.
In applications where extending the acquisition time is desired, the user can make use of the ADC acquisition extension
bits (ADCN.ADACQ[3:0]). When the ADC acquisition extension is enabled (ADACQEN = 1), the sample is acquired
over a prolonged period. The extended acquisition time is determined by ADACQ[3:0] and the ADC clock divider used.
Table 6-1 shows the extended acquisition time in terms of ADC clocks at different ADACQ[3:0] and clock divider set-
tings. The total acquisition time, ACQ, is the extended acquisition time (ADACQ, as listed in Table 6-1) plus three ADC
clock cycles. Figure 6-2 shows the clocking required for one conversion.
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