Maxim-integrated MAXQ Family Users Guide: MAXQ2000 Supplement Bedienungsanleitung Seite 1

Functional DiagramsPin Configurations appear at end of data sheet.Functional Diagrams continued at end of data sheet.UCSP is a trademark of Maxim Inte

MAXQ Family User’s Guide:MAXQ2000 Supplement32k x 16PROGRAM FLASHOR MASKED ROMPROGRAMSPACEEXECUTING FROMDATA SPACE(BYTE MODE)DATA SPACE(WORD MODE)0000

MAXQ Family User’s Guide:MAXQ2000 SupplementClock GenerationAll functional modules in the MAXQ2000 are synchronized to a single system clock. This sys

MAXQ Family User’s Guide:MAXQ2000 SupplementTable 1. System Clock Generation and Control RegistersExternal High-Frequency Oscillator Circuit or ClockT

To select the ring oscillator as the system clock source, the RGSL bit (CKCN.6) must be set to 1. Setting this bit immediately switchesover the syste

MAXQ Family User’s Guide:MAXQ2000 SupplementTable 2. MAXQ2000 Interrupt Sources and Control BitsINTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT

MAXQ Family User’s Guide:MAXQ2000 SupplementTable 2. MAXQ2000 Interrupt Sources and Control Bits (continued)INTERRUPT MODULE ENABLE BIT LOCAL ENABLE B

MAXQ Family User’s Guide:MAXQ2000 SupplementReset ConditionsThere are three possible reset sources for the MAXQ2000. While in the reset state, the ena

Power Management FeaturesThe MAXQ2000 provides the following features to assist in power management.• Divide-by-256 (PMM1) and 32kHz (PMM2) modes to r

MAXQ Family User’s Guide:MAXQ2000 SupplementThis power management mode is entered by setting the PMME bit (CKCN.2) to 1 while the CD1 and CD0 (CKCN[1:

Note that exiting Stop mode through external reset or power-on reset causes the processor to undergo a normal reset cycle, asopposed to resuming execu

MAXQ Family User’s Guide:MAXQ2000 SupplementPower Management Features 17Divide-by-256 Mode (PMM1) 1732kHz Mode (PMM2) 18Switchback Mode 18Stop Mode 18

MAXQ Family User’s Guide:MAXQ2000 SupplementTable 5. System Register Bit FunctionsREGBIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6

Table 6. System Register Reset ValuesMAXQ Family User’s Guide:MAXQ2000 SupplementREGBIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6

MAXQ Family User’s Guide:MAXQ2000 SupplementThe following section details the functionality of any System Registers contained in the MAXQ2000 that ope

Bits 5 and 6: (SC.5 and SC.6) ReservedBit 7: (SC.7) Test Access (JTAG) Port Enable0 = JTAG TAP functions are disabled and P4.0 through P4.3 can be use

MAXQ Family User’s Guide:MAXQ2000 SupplementMAXQ2000 System Clock ModesBit 0: (CKCN.0) Clock Divide 0 (CD0); Bit 1: (CKCN.1) Clock Divide 1 (CD1); Bit

Bit 3: (CKCN.3) Switchback Enable (SWB). Setting this bit to 1 enables Switchback mode. If power management mode (either divideby 256 or 32kHz) is act

MAXQ Family User’s Guide:MAXQ2000 SupplementADDENDUM TO SECTION 5: PERIPHERAL REGISTER MODULESRefer to the MAXQ Family User’s Guide.Table 7. Periphera

MAXQ Family User’s Guide:MAXQ2000 SupplementREG BIT 15BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0PO0

MAXQ Family User’s Guide:MAXQ2000 SupplementREG BIT15BIT14BIT13BIT12BIT11BIT 10BIT 9BIT 8BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0PD6PD6 (8 bits)PD7— —

MAXQ Family User’s Guide:MAXQ2000 SupplementREGBIT15BIT14 BIT13 BIT12 BIT11BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0T2CH0T2C0.

ADDENDUM TO SECTION 17: IN-SYSTEM PROGRAMMING (JTAG) 57Bootloader Protocol 58Family 0 Commands (Not Password Protected) 59Family 1 Commands: Load Vari

MAXQ Family User’s Guide:MAXQ2000 SupplementREGBIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0PO0

MAXQ Family User’s Guide:MAXQ2000 SupplementREGBIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1BIT 0PD6

MAXQ Family User’s Guide:MAXQ2000 SupplementREGBIT 15BIT 14BIT 13BIT 12BIT 11BIT 10BIT 9BIT 8BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0T2RH000000000T2CH

MAXQ Family User’s Guide:MAXQ2000 SupplementADDENDUM TO SECTION 6: GENERAL-PURPOSE I/O MODULE(GPIO AND EXTERNAL INTERRUPTS)The MAXQ2000 provides 50 po

MAXQ Family User’s Guide:MAXQ2000 SupplementPORT PIN TYPE SPECIAL FUNCTION ENABLED WHEN P3.1 Analog LCD Segment SEG25 PCF3=1 and OPM=1 P3.2 Analog

MAXQ Family User’s Guide:MAXQ2000 SupplementPORT PIN TYPE SPECIAL FUNCTION ENABLED WHENP0.0 Analog LCD Segment SEG0 PCF0=1 and OPM=1P0.1 Analog LCD Se

MAXQ Family User’s Guide:MAXQ2000 SupplementThe port pins on the MAXQ2000 operate the same as standard MAXQ port pins, with input/output states define

The following peripheral registers control the general-purpose I/O and external interrupt features specific to the MAXQ2000.Register Name: PO0Register

MAXQ Family User’s Guide:MAXQ2000 SupplementRegister Name: PO3Register Description: Port 3 Output RegisterRegister Address: M0[03h]Bits 0 to 7: (PO3.0

Bit 0: (EIE0.0) External Interrupt 0 Enable (EX0)Bit 1: (EIE0.1) External Interrupt 1 Enable (EX1)Bit 2: (EIE0.2) External Interrupt 2 Enable (EX2)Bit

MAXQ Family User’s Guide:MAXQ2000 SupplementFigure 1. MAXQ2000 System and Peripheral Register Map 8Figure 2. Memory Map When Executing from Applicatio

MAXQ Family User’s Guide:MAXQ2000 SupplementRegister Name: PI3Register Description: Port 3 Input RegisterRegister Address: M0[0Bh]Each of the read-onl

Register Name: PD1Register Description: Port 1 Direction RegisterRegister Address: M0[11h]Each of the bits in this register controls the input/output

MAXQ Family User’s Guide:MAXQ2000 SupplementRegister Name: PO4Register Description: Port 4 Output RegisterRegister Address: M1[00h]Bits 0 to 4: (PO4.0

Register Name: PO7Register Description: Port 7 Output RegisterRegister Address: M1[03h]Bits 0 and 1: (PO7.0 and PO7.1) Port Output for P7.0 and P7.1.

MAXQ Family User’s Guide:MAXQ2000 SupplementRegister Name: EIE1Register Description: External Interrupt Enable 1 RegisterRegister Address: M1[07h]Each

Register Name: PI6Register Description: Port 6 Input RegisterRegister Address: M1[0Ah]Bits 0 to 7: (PI6.0 to PI6.7) Port Pin Input Bits for P6.0 to P6

MAXQ Family User’s Guide:MAXQ2000 SupplementRegister Name: PD4Register Description: Port 4 Direction RegisterRegister Address: M1[10h]Bits 0 to 4: (PD

Register Name: PD7Register Description: Port 7 Direction RegisterRegister Address: M1[13h]Bits 0 and 1: (PD7.0 and PD7.1) Port Direction Bits for P7.0

MAXQ Family User’s Guide:MAXQ2000 SupplementRegister Name: WKORegister Description: Wakeup Output RegisterRegister Address: M1[1Fh]Bit 0: (WKO.0) Wake

ADDENDUM TO SECTION 7: TIMER/COUNTER 0 MODULEThe MAXQ2000 does not provide these peripherals. Refer to the MAXQ Family User’s Guide.ADDENDUM TO SECTIO

Table 1. System Clock Generation and Control Registers 12Table 2. MAXQ2000 Interrupt Sources and Control Bits 14Table 3. System Power Management Regis

Timer 2 Example: Triggering a Periodic Interruptmove PD0, #0FFh ; Set P0.0-P0.7 to output modemove PO0, #000h ; Drive low on all Port 0 pinsmove

ADDENDUM TO SECTION 10: SERIAL I/O (UART) MODULEThe MAXQ2000 provides up to two serial UART modules (Serial 0 and 1 in the 68-pin package, Serial 0 in

MAXQ Family User’s Guide:MAXQ2000 SupplementADDENDUM TO SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI)The MAXQ2000 provides a Serial Peripheral Interfa

ADDENDUM TO SECTION 12: HARDWARE MULTIPLIERThe MAXQ2000 provides a hardware multiplier module that provides the following features (detailed in the MA

MAXQ Family User’s Guide:MAXQ2000 SupplementADDENDUM TO SECTION 13: 1-Wire BUS MASTERThe MAXQ2000 provides a 1-Wire Bus Master (68-pin package only) t

1-Wire Example: Reset and Presence DetectOW_COMMAND equ 00hOW_BUFFER equ 01hOW_INTERRUPT equ 02hOW_INT_ENABLE equ 03hOW_CLOCK equ 04hOW_C

MAXQ Family User’s Guide:MAXQ2000 SupplementADDENDUM TO SECTION 15: TEST ACCESS PORT (TAP)The JTAG TAP port on the MAXQ2000 is multiplexed with port p

The first byte output by this command is the value 146 (092h), which represents the number of peripheral registers output. Table 25lists the remaining

MAXQ Family User’s Guide:MAXQ2000 SupplementBit 1: (ICDF.1) System Program Enable (SPE). This bit controls the behavior of the MAXQ2000 following rese

All commands in Family 0 can be executed without first matching the password. All other commands (in Families 1x through Fx) arepassword protected; th

MAXQ Family User’s Guide:MAXQ2000 SupplementTable 32. LCD Display Memory Map (Static, 56-Pin Package) 76Table 33. LCD Display Memory Map (1/2 Duty, 56

MAXQ Family User’s Guide:MAXQ2000 SupplementCommand 05h—Get Supported CommandsThe SupportL (LSB) and SupportH (MSB) bytes form a 16-bit value that ind

Command 09h—Get Utility ROM VersionCommand 0Ah—Set Word/Byte Mode AccessThe Mode byte should be 0 to set byte access mode or 1 to set word access mode

MAXQ Family User’s Guide:MAXQ2000 SupplementFamily 2 Commands: Dump Variable Length (Password Protected)Command 20h—Dump Code Variable LengthThis comm

Family 4 Commands: Verify Variable Length (Password Protected)Command 40h—Verify Code Variable LengthThis command operates in the same manner as the “

MAXQ Family User’s Guide:MAXQ2000 SupplementFamily E Commands: Erase Fixed Length (Password Protected)Command E0h—Erase Code Fixed LengthThis command

MAXQ Family User’s Guide:MAXQ2000 SupplementMNEMONIC DESCRIPTION16-BIT INSTRUCTIONWORDSTATUS BITSAFFECTEDAPINC/DECNOTESADD src Acc ← Acc + src f100 10

LCD CONTROLLER (SPECIFIC TO MAXQ2000)The MAXQ2000 provides an on-board LCD controller module that can generate segment and common signals for an LCD b

The following peripheral registers are used to control the LCD controller.Register Name: LCFGRegister Description: LCD Configuration RegisterRegister

Register Name: LCRARegister Description: LCD Adjust RegisterRegister Address: M2[0Dh]This register can only be written to when the LCD controller is i

The following registers (LCD0 to LCD15) contain display memory for the LCD controller.Register Name: LCD0Register Description: LCD Display Register 0R

ADDENDUM TO SECTION 1: OVERVIEWThe MAXQ2000 is a low-power, high-performance 16-bit RISC microcontroller based on the MAXQ™ architecture. It includes

Register Name: LCD4Register Description: LCD Display Register 4Register Address: M2[14h]Register Name: LCD5Register Description: LCD Display Register

Register Name: LCD8Register Description: LCD Display Register 8Register Address: M2[18h]Register Name: LCD9Register Description: LCD Display Register

Register Name: LCD12Register Description: LCD Display Register 12Register Address: M2[1Ch]Register Name: LCD13Register Description: LCD Display Regist

MAXQ Family User’s Guide:MAXQ2000 SupplementSTATIC DISPLAYRRVLCD2VADJRVLCDVLCD1RADJGNDIOLRIG1/2 BIASRRVLCD2VADJRVLCDVLCD1RADJGNDIOLRIG1/3 BIASRRVLCD2V

MAXQ Family User’s Guide:MAXQ2000 SupplementSTATIC DISPLAYRRVLCD2VADJRVLCDVLCD1RADJGNDIOLRIG = 1STATIC DISPLAYRRVLCD2VADJRVLCDVLCD1RADJGNDIOLRIG = 0RE

LCD Frame FrequencyThe LCD controller clock frequency (fLCD) can be sourced from either the 32kHz clock or the high-frequency clock divided by 128 ass

MAXQ Family User’s Guide:MAXQ2000 SupplementREGISTERBIT 7COM0BIT 6COM0BIT 5COM0BIT 4COM0BIT 3COM0BIT 2COM0BIT 1COM0BIT 0COM0LCD0 SEG7 SEG6 SEG5 SEG4 S

MAXQ Family User’s Guide:MAXQ2000 SupplementREGISTER BIT 7BIT 6COM2BIT 5COM1BIT 4COM0BIT 3BIT 2COM2BIT 1COM1BIT 0COM0LCD0 SEG1 SEG1 SEG1 SEG0 SEG0 SEG

MAXQ Family User’s Guide:MAXQ2000 SupplementREGISTERBIT 7COM0BIT 6COM0BIT 5COM0BIT 4COM0BIT 3COM0BIT 2COM0BIT 1COM0BIT 0COM0LCD0 SEG7 SEG6 SEG5 SEG4 S

MAXQ Family User’s Guide:MAXQ2000 SupplementREGISTER BIT 7BIT 6COM2BIT 5COM1BIT 4COM0BIT 3BIT 2COM2BIT 1COM1BIT 0COM0LCD0 SEG1 SEG1 SEG1 SEG0 SEG0 SEG

MAXQ Family User’s Guide:MAXQ2000 Supplement• 1-Wire Interface Master• LCD Controller (up to 132 segments)The lower 8 bits of all registers in modules

Display Waveform GenerationOnce the operational modes and display memory registers on the LCD controller have been properly initialized, the controlle

Table 40. Static Drive Example Common Signal SelectionAccording to the static memory map table, a value of 0F6h should be written to the LCD0 register

LCD Controller 1/2 Duty Cycle Drive ExampleIn this example, SEG0 through SEG3 are used to drive the LCD segments. The segments and common signals are

MAXQ Family User’s Guide:MAXQ2000 SupplementCOM1COM2COM0SEG2SEG1SEG0Figure 16. 1/3 Drive Example Display Connection1 FRAME (fFRAME)VLCDVLCD1GNDCOM0VLC

Table 44. 1/3 Duty Drive Example Common Signal SelectionAccording to the 1/3 duty drive memory map table, LCD0 should be set to 071h and LCD1 should b

LCD Controller 1/4 Duty Cycle Drive ExampleIn this example, SEG0 and SEG1 are used to drive the LCD segments. The segments and common signals are conn

MAXQ Family User’s Guide:MAXQ2000 Supplement1 FRAME (fFRAME)VLCDVLCD1VLCD2GNDSEG1VLCDVLCD1VLCD2GNDSEG0VLCDVLCD1VLCD2GNDCOM2VLCDVLCD1VLCD2GNDCOM1VLCDVL

UTILITY ROM (SPECIFIC TO MAXQ2000)The MAXQ2000 utility ROM includes routines that provide the following functions to application software.• In-applica

MAXQ Family User’s Guide:MAXQ2000 SupplementFunction: flashErasePage Summary: Erases (programs to 0FFFFh) a 256-word page of flash memory. Inputs: A

MAXQ Family User’s Guide:MAXQ2000 SupplementFunction: moveDP0dec Summary: Reads the byte/word value pointed to by DP[0], then decrements DP[0]. Inpu

Memory OrganizationAs with all MAXQ microcontrollers, the MAXQ2000 contains logically separate program and data memory spaces. All memory is inter-nal

MAXQ Family User’s Guide:MAXQ2000 SupplementFunction: moveFP Summary: Reads the byte/word value pointed to by BP[Offs].Inputs: BP[Offs]: Address to r

MAXQ Family User’s Guide:MAXQ2000 SupplementROM Example 1: Calling A Utility ROM Function DirectlyThis example shows the direct addressing method for

MAXQ Family User’s Guide:MAXQ2000 SupplementROM Example 2: Calling A Utility ROM Function IndirectlyThe second example shows the indirect addressing m

MAXQ Family User’s Guide:MAXQ2000 SupplementREVISION HISTORYRev 0; 10/04: Original release.Rev 1; 10/05: Family Commands section updated. Commands 11h