Maxim-integrated MAXQ610 Bedienungsanleitung PDF herunterladen (Seite 7)

2-3

MAXQ610 User’s Guide

SECTION 2: ARCHITECTURE

The MAXQ610 is designed to be modular and expandable. Top-level instruction decoding is extremely simple and

based on transfers to and from registers. The registers are organized into functional modules, which are in turn divided

into the system register and peripheral register groups. Figure 2-1 illustrates the modular architecture and the basic

transport possibilities.

Figure 2-1. MAXQ610 Transport-Triggered Architecture

SYSTEM MODULES/

REGISTERS

PERIPHERAL MODULES/REGISTERS

DATA

MEMORY

dst

ADDITIONAL MODULES

FOR FUTURE EXPANSION

STACK

MEMORY

CKCN

WDCN

ADDRESS

GENERATION

LOOP COUNTERS

LC[

IPR0

INTERRUPT

LOGIC

CLOCK CONTROL,

WATCHDOG TIMER

AND POWER MONITOR

BOOLEAN

VARIABLE

MANIPULATION

ACCUMULATORS

(16)

APC

PSF

INSTRUCTION

DECODE

(src, dst TRANSPORT

DETERMINATION)

MUX

DATA POINTERS

DP[0], DP[1]

FP =

(BP + OFFS)

DPC

MEMORY MANAGEMENT

UNIT (MMU)

PROGRAM

MEMORY

src

dst

src

GENERAL-

PURPOSE

I/O

TIMERS/

COUNTERS

USART

AND SPI

1 2 3 4 5 6 7 8 9 10 11 12 ... 202 203

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