Maxim-integrated DS4830 Optical Microcontroller Bedienungsanleitung Seite 163
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DS4830 User’s Guide
163
Table 21-4. Output from Read Register Map Command
WORD
REGISTER
WORD
REGISTER
WORD
REGISTER
WORD
REGISTER
WORD
REGISTER
WORD
REGISTER
WORD
REGISTER
0
PO2
32
64
96
MCNT
128
DACD0
160
192
A[3]
1
PO1
33
I2CST-M
65
I2CST-S
97
MA
129
DACD1
161
QTCN
193
A[4]
2
PO0
34
I2CIE-M
66
I2CIE-S
98
MB
130
DACD2
162
LTIF
194
A[5]
3
EIF2
35
PO6
67
ADCN
99
MC2
131
DACD3
163
HTIF
195
A6[]
4
EIF1
36
68
DADDR
100
MC1
132
DACD4
164
196
A[7]
5
EIF0
37
MIIR1
69
SENR
101
MC0
133
DACD5
165
197
A[8]
6
GTV1
38
EIF6
70
ADST
102
GTV2
134
DACD5
166
PWMCN
198
A[9]
7
GTCN1
39
EIE6
71
ADADDR
103
GTCN2
135
DACD6
167
PWMSYNC
199
A[10]
8
PI2
40
PI6
72
MIIR2
104
MC1R
136
DACD7
168
LTIE
200
A[11]
9
PI1
41
SVM
73
105
MC0R
137
DACCFG
169
HTIE
201
A[12]
10
PI0
42
-
74
TWR
106
GTC2
138
170
QTLST
202
A[13]
11
GTC1
43
-
75
TEMPCN
107
139
171
203
A[14]
12
44
I2CCN-M
76
I2CCN-S
108
140
172
204
A[15]
13
EIE2
45
I2CCK-M
77
I2CCK-S
109
141
173
205
IP
14
EIE1
46
I2CTO-M
78
I2CTO-S
110
142
174
206
SP
15
EIE0
47
I2CSLA-M
79
I2CSLA-S
111
143
175
207
IV
16
PD2
48
EIES6
80
SHCN
112
144
176
208
LC[0]
17
PD1
49
PD6
81
113
145
177
209
LC[1]
18
PD0
50
SPICN_S
82
PINSEL
114
146
178
SPICN_M
210
OFFS
19
EIES2
51
SPICF_S
83
115
147
179
SPICF_M
211
DPC
20
EIES1
52
SPICK_S
84
116
148
180
SPICK_M
212
GR
21
EIES0
53
85
I2C_SPB
117
149
181
213
BP
22
54
ETS
86
-
118
150
182
214
DP[0]
23
55
ADCG1
87
119
151
183
215
DP[1]
24
56
ADCG2
88
ICDT0
120
152
184
AP
APC
25
57
ADVOFF
89
ICDT1
121
153
185
PSF
IC
26
58
TOEX
90
ICDC
122
154
186
IMR
SC
27
59
ADCG3
91
ICDF
123
155
187
IIR
CKCN
28
60
ADCG4
92
ICDB
124
156
188
WDCN
0
29
61
CHIPREV
93
ICDA
125
157
189
A[0]
30
62
94
ICDD
126
158
190
A[1]
31
63
95
127
159
191
A[2]
21.2.3 – Single Step Operation (Trace)
The debug engine supports single step operation in debug mode by executing a Trace command from the host. The
debug engine allows the CPU to return to its normal program execution for one cycle and then forces a debug mode re-
entry. The steps for the Trace command are:
1) Set status to 10b (debug-busy)
2) Pop the return address from the stack
3) Set the IGE bit to logic 1 if debug mode was activated when IGE=1.
4) Supply the CPU with an instruction addressed by the return address
5) Stall the CPU at the end of the instruction execution
6) Block the next instruction fetch from program memory
7) Push the return address onto the stack
8) Set the contents of IP to x8010h
9) Clear the IGE bit to 0 to disable the interrupt handler
10) Halt CPU operation
11) Set the status to debug-idle
Note that the trace operation uses a return address from the stack as a legitimate address for program fetching. The host
must maintain consistency of program flow during the debug process. The Instruction Pointer is automatically incremented
after each trace operation, thus a new return address will be pushed onto the stack before returning the control to the
- OpticalMicrocontroller 1
- User’sGuide 1
- Contents 2
- SECTION 1 – OVERVIEW 9
- DS4830 User’s Guide 10
- SECTION 2 – ARCHITECTURE 11
- 2.2 – Register Space 12
- 2.3 – Memory Types 13
- 2.5 – Data Alignment 20
- 2.6 – Reset Conditions 20
- 2.7 – Clock Generation 22
- SECTION 5 – INTERRUPTS 36
- 5.1 – Servicing Interrupts 37
- 6.1 – Detailed Description 42
- 6.3 – DAC Code Examples 45
- 7.1 – Detailed Description 46
- 7.3 – ADC Code Examples 58
- SECTION 8 – SAMPLE AND HOLD 60
- 9.1 – Detailed Description 68
- SECTION 10 – I 76
- SECTION 11 – I 89
- C-COMPATIBLE SLAVE INTERFACE 89
- 11.1 – Detailed Description 90
- 12.2 – SPI System Errors 101
- 12.3 – SPI Interrupts 102
- SECTION 13 – 3-WIRE 110
- Using PWMCN and PWMDATA 113
- Core Clock 120
- FrequencyClockPWM 123
- FrequencyFramePWM 123
- * = 01b 127
- MULTIPLIER 140
- SECTION 19 – WATCHDOG TIMER 146
- 20.1 – TAP Controller 150
- 20.2 – TAP State Control 151
- 20.3 – Communication via TAP 152
- 21.2 – Debug Mode 160
- 22.1 – Detailed Description 169
- 22.2 – Bootloader Operation 171
- 22.3 – Bootloader Commands 173
- SECTION 23 – PROGRAMMING 179
- SECTION 24 – INSTRUCTION SET 192
- SECTION 25 – UTILITY ROM 220
- 25.4 – Utility ROM Examples 227
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