Maxim-integrated DS4830 Optical Microcontroller Bedienungsanleitung PDF herunterladen (Seite 67)

DS4830 User’s Guide

8.2.2 – Sample and Hold Internal Trigger Enable Register (SENR)

SENR Register Address: M2[05h]

Bit

Name

INT_TRIG_EN1

INT_TRIG1

INT_TRIG_EN0

INT_TRIG0

Reset

Access

BIT

NAME

DESCRIPTION

15:6

Reserved. The user should write 0 to these bits.

INT_TRIG_EN1

Sample and Hold 1 Internal Trigger Enable. Setting this bit to ‘1’ will enable internal

trigger mode for Sample and Hold 1. When this bit is set to ‘1’, writing a ‘1’ to INT_TRIG1

will start an internal sample pulse for Sample and Hold 1. When this bit is ‘1’, sample

pulses on SHEN1 are rejected.

Setting this bit to ‘0’ will configure Sample and Hold 1 for external sample pulse.

This bit is used in the dual mode operation only.

INT_TRIG1

Sample and Hold 1 Internal Trigger. This bit is used when the INT_TRIG_EN1 is set to

‘1’. Setting this bit to ‘1’ will start internal sample pulse for Sample and Hold 1. Depending

upon the SSC[3:0] bit setting, the sample pulse will stop when this bit is set to ‘0’. This bit

is used in the dual mode operation only.

3:2

Reserved. The user should write 0 to these bits.

INT_TRIG_EN0

Sample and Hold Internal Trigger Enable. Setting this bit to ‘1’ will enable internal

trigger mode for Sample and Hold 0. When this bit is set to ‘1’, writing a ‘1’ to INT_TRIG0

will start an internal sample pulse for Sample and Hold 0. When this bit is ‘1’, sample

pulses on SHEN0 are rejected.

Setting this bit to ‘0’ will configure Sample and Hold 0 for external sample pulse.

In the single mode operation, this bit is used for both sample and holds.

INT_TRIG0

Sample and Hold0 Internal Trigger. This bit is used when the INT_TRIG_EN0 is set to

‘1’. Setting this bit to ‘1’ will start internal sample pulse for Sample and Hold 0. Depending

upon the SSC[3:0] bit setting, the sample pulse will stop when this bit is set to ‘0’.

In the single mode operation, this bit is used for both sample and holds.

8.2.3 – Sample and Hold Interrupt flag

See ADST description for Sample and Hold interrupts flags SH0DAI and SH1DAI descriptions.

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