Maxim-integrated DS80C390 Bedienungsanleitung Seite 26
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DS80C390
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Each of the message centers is identical with the exception of message center 15. Message center 15 has
been designed as a receive only center and is also buffered through the use of a two message FIFO to help
prevent message loss in a message overrun situation. The receipt of a third message before either of the
first two are read will overwrite the second message, leaving the first message undisturbed.
Modification of the CAN registers located in MOVX memory is protected via the SWINT bits, with one
bit protecting each respective CAN module. Consult the description of this bit in the User’s Guide for
more information. Each CAN Module contains a block of Control/Status/Mask registers, 14 functionally
identical message centers, plus a fifteenth message center which is receive only and incorporates a
buffered FIFO. The following tables describe the organization of the message centers located in MOVX
space.
MOVX MESSAGE CENTERS FOR CAN 0
CAN 0 CONTROL/STATUS/MASK REGISTERS
Register 7 6 5 4 3 2 1 0
MOVX Data
Address
1
C0MID0 MID07 MID06 MID05 MID04 MID03 MID02 MID01 MID00 xxxx00h
C0MA0 M0AA7 M0AA6 M0AA5 M0AA4 M0AA3 M0AA2 M0AA1 M0AA0 xxxx01h
C0MID1 MID17 MID16 MID15 MID14 MID13 MID12 MID11 MID10 xxxx02h
C0MA1 M1AA7 M1AA6 M1AA5 M1AA4 M1AA3 M1AA2 M1AA1 M1AA0 xxxx03h
C0BT0 SJW1 SJW0 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 xxxx04h
C0BT1 SMP TSEG26 TSEG25 TSEG24 TSEG13 TSEG12 TSEG11 TSEG10 xxxx05h
C0SGM0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 xxxx06h
C0SGM1 ID20 ID19 ID18 0 0 0 0 0 xxxx07h
C0EGM0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 xxxx08h
C0EGM1 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 xxxx09h
C0EGM2 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 xxxx0Ah
C0EGM3 ID4 ID3 ID2 ID1 ID0 0 0 0 xxxx0Bh
C0M15M0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 xxxx0Ch
C0M15M1 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 xxxx0Dh
C0M15M2 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 xxxx0Eh
C0M15M3 ID4 ID3 ID2 ID1 ID0 0 0 0 xxxx0Fh
CAN 0 MESSAGE CENTER 1
Reserved xxxx10h - 11h
C0M1AR0 CAN 0 MESSAGE 1 ARBITRATION REGISTER 0 xxxx12h
C0M1AR1 CAN 0 MESSAGE 1 ARBITRATION REGISTER 1 xxxx13h
C0M1AR2 CAN 0 MESSAGE 1 ARBITRATION REGISTER 2 xxxx14h
C0M1AR3 CAN 0 MESSAGE 1 ARBITRATION REGISTER 3 WTOE xxxx15h
C0M1F DTBYC3DTBYC2DTBYC1DTBYC0
T/
R
EX/ ST
MEME MDME xxxx16h
C0M1D0-7 CAN 0 MESSAGE 1 DATA BYTES 0 - 7 xxxx17h - 1Eh
Reserved xxxx1Fh
- DS80C390 1
- Dual CAN High-Speed 1
- Microprocessor 1
- DESCRIPTION 2
- ORDERING INFORMATION 2
- 3 of 58 110199 3
- PIN DESCRIPTION Table 1 4
- INT0 External Interrupt 0 5
- INT1 External Interrupt 1 5
- 80C32 COMPATIBILITY 7
- PERFORMANCE OVERVIEW 7
- INSTRUCTION SET SUMMARY 7
- SPECIAL FUNCTION REGISTERS 8
- 9 of 58 110199 9
- 40-BIT ACCUMULATOR 11
- MEMORY ADDRESSING 12
- INTERNAL MOVX SRAM 13
- EXTERNAL MEMORY ADDRESSING 13
- STRETCH MEMORY CYCLES 14
- EXTENDED STACK POINTER 15
- ENHANCED DUAL DATA POINTERS 16
- SYSTEM CLOCK CONTROL 17
- OSCILLATOR FAIL DETECT 18
- POWER MANAGEMENT MODE (PMM) 19
- SWITCHBACK 19
- IDLE MODE 20
- STOP MODE 20
- BAND-GAP SELECT 20
- RING OSCILLATOR 20
- TIMED ACCESS PROTECTION 21
- EMI REDUCTION 22
- PERIPHERAL OVERVIEW 22
- SERIAL PORTS 22
- WATCHDOG TIMER 22
- EXTERNAL RESET PINS 24
- INTERRUPTS 24
- INTERRUPT SUMMARY Table 12 24
- Register 7 6 5 4 3 2 1 0 28
- CAN INTERRUPTS 29
- ARBITRATION AND MASKING 29
- MESSAGE BUFFERING/OVERWRITE 30
- BIT TIMING 31
- ABSOLUTE MAXIMUM RATINGS* 32
- DC ELECTRICAL CHARACTERISTICS 32
- TYPICAL I 33
- VERSUS FREQUENCY 33
- 4CE0 − Valid to ALE Low 34
- 4CE0 − , 4PCE0− Valid to 35
- TIME PERIODS 36
- 37 of 58 110199 37
- 38 of 58 110199 38
- 3-PCE0 READ OR WRITE 39
- 3-CE0 READ 39
- 3-CE0 WRITE 40
- 44 of 58 110199 44
- RD Pulse Width 45
- RD Low to Valid Data In 45
- RD or WR Low 45
- RD or WR 45
- 46 of 58 110199 46
- 47 of 58 110199 47
- 54 of 58 110199 54
- WR signal 55
- 68-PIN PLCC 56
- 64-PIN LQFP 57
- DATA SHEET REVISION SUMMARY 58
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