Maxim-integrated MAXQ7666 Bedienungsanleitung PDF herunterladen (Seite 143)

MAXQ7665/MAXQ7666 User’s Guide

4-13

CAN 0 Standard Global Mask Register 0 (C0SGM0)

CAN 0 Standard Global Mask Register 1 (C0SGM1)

CAN Standard Global Mask Registers 0 and 1 (C0SGM0 and C0SGM1). These registers function as the mask when performing the

11-bit global identification test on incoming messages for message centers 1–14. If message identification masking is disabled (MEME

= 0), the incoming message ID field must match the corresponding message center arbitration value exactly, effectively ignoring the

contents of these registers. These registers are only used when performing the message identification test for message centers con-

figured as standard receivers (EX/ST = 0) having message ID masking enabled (MEME = 1). Thus, the contents are ignored by mes-

sage centers configured to receive messages with extended identifiers (EX/ST = 1). These registers can only be modified during a soft-

ware initialization (SWINT = 1).

When MEME = 1, any mask bit in the C0SGM1, C0SGM0 mask programmed to 0 creates a don’t care condition when the respective

bit in the incoming message ID field is compared with the corresponding arbitration bits in message centers 1–14. Any bit in these

masks programmed to a 1 forces the respective bit in the incoming message ID field to match identically with the corresponding arbi-

tration bits in message centers 1–14 before said message is loaded into message centers 1–14.

The five least significant bits in the C0SGM1 register are not used and do not perform any comparison of these bit locations. A read

of these bits will return 0, writes are ignored.

CAN 0 Extended Global Mask Register 0 (C0EGM0)

Bit #

7 6 5 4 3 2 1 0

Name MASK28 MASK27 MASK26 MASK25 MASK24 MASK23 MASK22 MASK21

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw rw rw rw rw

Dual Port

Address

03h(L)

Bit #

7 6 5 4 3 2 1 0

Name MASK28 MASK27 MASK26 MASK25 MASK24 MASK23 MASK22 MASK21

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw rw rw rw rw

Dual Port

Address

04h(L)

Bit #

7 6 5 4 3 2 1 0

Name MASK20 MASK19 MASK18 — — — — —

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw rw rw rw rw

Dual Port

Address

03h(H)

r = read, w = write (allowed only when SWINT = 1 via C0DP/C0DB)

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