Maxim-integrated MAXQ622 Bedienungsanleitung Seite 1

MAXQ612/MAXQ622 USER’S GUIDE For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrat

MAXQ612/MAXQ622 User’s Guide2-6 Maxim Integrated2.3 Memory OrganizationBeyond the internal register space, memory on the MAXQ612/MAXQ622 microcontrol

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-27REGISTER DESCRIPTIONI2CST.14 (I2CBUSY) I2C Busy. This bit is used to indicate the current status of

MAXQ612/MAXQ622 User’s Guide5-28 Maxim IntegratedREGISTER DESCRIPTIONI2CIE.11 (I2CSPIE) I2C STOP Interrupt Enable. Setting this bit to 1 causes an in

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-29REGISTER DESCRIPTIONI2CCK (08h, 04h) I2C Clock Control Register (16-bit register)Initialization: Th

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 6-16.1 Port Pin Register Descriptions ...6

MAXQ612/MAXQ622 User’s Guide6-2 Maxim IntegratedSECTION 6: GENERAL-PURPOSE I/O MODULEThe MAXQ612/MAXQ622 provide 38 port pins for general-purpose I/O

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 6-3All these special functions are disabled by default with the exception of the JTAG interface pins, w

MAXQ612/MAXQ622 User’s Guide6-4 Maxim Integrated6.1 Port Pin Register DescriptionsThe following peripheral registers are used to control the general-

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 6-5Bits 7:0: Port 3 Output. This register stores the data that is output on any of the pins of port 3 t

MAXQ612/MAXQ622 User’s Guide6-6 Maxim IntegratedBits 7:0: Port 0 Input Bits. The read values of these bits reflect the logic states present at port 0

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 6-7Bits 7:0: Port 4 Input Bits. The read values of these bits reflect the logic states present at port

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-7Following each reset, the processor automatically starts execution at address 8000h in the utility R

MAXQ612/MAXQ622 User’s Guide6-8 Maxim IntegratedBits 7:0: Input/Output Direction for Port 1. The bits in this register control the input/output direc

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 6-9Bits 5:0: Input/Output Direction for Port 5. The bits in this register control the input/output dire

MAXQ612/MAXQ622 User’s Guide6-10 Maxim Integrated6.2 External Interrupt Register DescriptionsEach bit in this register is set when a negative edge or

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 6-11Each bit in this register controls the enable for one external interrupt. If a bit is set to 1, the

MAXQ612/MAXQ622 User’s Guide6-12 Maxim IntegratedEach bit in this register controls the edge select mode for an external interrupt, as follows:0 = Th

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 7-17.1 Timer B...7-27.1.

MAXQ612/MAXQ622 User’s Guide7-2 Maxim IntegratedSECTION 7: TIMER/COUNTER TYPE BThe timer/counter module allows the MAXQ612/MAXQ622 to control a 16-

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 7-37.1.2 Timer B Mode: Capture ModeThe 16-bit capture mode is invoked by setting the CP/RLB (TBCN.0) bi

MAXQ612/MAXQ622 User’s Guide7-4 Maxim Integrated7.1.3 Timer B Mode: Up/Down Autoreload ModeThe up/down-count autoreload option is enabled by the DCEN

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 7-57.1.5 Timer B Mode: PWM Output FunctionThe PWM output function is enabled whenever the TBCS:TBCR bit

MAXQ612/MAXQ622 User’s Guide2-8 Maxim Integrated2.3.4 Stack MemoryThe MAXQ612/MAXQ622 implement a soft stack that uses the on-chip data memory (SRAM)

MAXQ612/MAXQ622 User’s Guide7-6 Maxim Integrated7.1.5.1 Timer B Mode: Up-Counting PWM Output ModeThe 16-bit timer/counter with autoreload mode is use

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 7-7The set and reset functions for the autoreload up-counting mode essentially provide the same functio

MAXQ612/MAXQ622 User’s Guide7-8 Maxim IntegratedExample TBB output waveforms for the autoreload up/down-counting modes are shown below.Up/down-count

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 7-9Bits 12 and 11: TBB Pin Output Reset Mode, Set Mode (TBCS:TBCR). These mode bits define whether the

MAXQ612/MAXQ622 User’s Guide7-10 Maxim Integrated7.2.2 Timer B Value Register (TBV)7.2.3 Timer B Capture/Reload Value Register (TBR)7.2.4 Timer B Com

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 8-18.1 Carrier Generation Module ...8-28

MAXQ612/MAXQ622 User’s Guide8-2 Maxim IntegratedSECTION 8: IR TIMERThe MAXQ612/MAXQ622 microcontroller provides a dedicated IR timer/counter module t

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 8-3Figure 8-1. IR Transmit Frequency Shifting Example (IRCFME = 0)Figure 8-2. IR Transmit Carrier Gener

MAXQ612/MAXQ622 User’s Guide8-4 Maxim IntegratedThe IR timer acts as a down counter in transmit mode. An IR transmission starts when the IREN bit is

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 8-58.4 IR ReceiveWhen configured in receive mode (IRMODE = 0), the IR hardware supports the IRRX captur

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-92.5.1 Memory Mapping Into Data SpaceThe MAXQ612/MAXQ622 map program memory into data space from 0000

MAXQ612/MAXQ622 User’s Guide8-6 Maxim IntegratedOn the first qualified event, it does the following:1) Captures the IRRX pin state and transfers it

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 8-7Figure 8-6. Receive Burst-Count ExampleIRRX12 356 84 7CARRIER FREQUENCYCALCULATIONIRMT = PULSE COUNT

MAXQ612/MAXQ622 User’s Guide8-8 Maxim IntegratedFigure 8-7. Philips Remote Encoding Example11 001 1 11 0 0 0 0011 0000 0 0IRDATAIRDATAIRRXIRRXSEL = 1

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 8-9Figure 8-8. Sony Remote Encoding Example1 101 10000011111 000000IRRXSEL = 10bIRMT_T IRMT_T IRMT_T IR

MAXQ612/MAXQ622 User’s Guide8-10 Maxim Integrated8.7 IR Timer Peripheral Registers8.7.1 IR Control Register (IRCN)Bit 13: IRV Count Enable (IRVCEN).

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 8-11Bits 5 and 4: IR Receive Edge Select Bits (IRRXSEL[1:0]) These bits define which edge of the input

MAXQ612/MAXQ622 User’s Guide8-12 Maxim IntegratedBit 1: IR Interrupt Flag (IRIF). This flag is set to 1 during transmit when the IR timer reloads its

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 9-19.1 USART Modes ...9-29.1.1

MAXQ612/MAXQ622 User’s Guide9-2 Maxim IntegratedSECTION 9: SERIAL I/O MODULEThe serial I/O module provides the MAXQ612/MAXQ622 access to a universal

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 9-3Figure 9-1. USART Mode 0DIVIDEBY 12D7D6D5D4D3D2D1D0LOADCLOCKOUTPUT SHIFT REGISTERS0LATCHRECEIVE DATA

MAXQ612/MAXQ622 User’s Guide2-10 Maxim IntegratedFigure 2-4. CDA Functions in Word ModePHYSICAL DATAx0000x8000x4000DATA MEMORY015015WORD MODE MEMORY

MAXQ612/MAXQ622 User’s Guide9-4 Maxim Integrated9.1.2 USART Mode 1This mode provides asynchronous, full-duplex communication. A total of 10 bits is t

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 9-5Figure 9-2. USART Mode 1DIVIDEBY 4D7D6D5D4D3D2D1D001LOADCLOCKTRANSMIT SHIFT REGISTERS0LATCHRECEIVE D

MAXQ612/MAXQ622 User’s Guide9-6 Maxim IntegratedData is sampled in a similar fashion to mode 1 with the majority voting on three consecutive samples.

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 9-79.1.4 USART Mode 3This mode has the same operation as mode 2, except for the baud rate source. As sh

MAXQ612/MAXQ622 User’s Guide9-8 Maxim Integrated9.2 Baud-Rate GenerationEach mode of operation has a baud-rate generator associated with it. The baud

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 9-9The below formulas can be used to calculate the output of the baud-clock generator and the resultant

MAXQ612/MAXQ622 User’s Guide9-10 Maxim IntegratedThe FE bit is set to a 1 when a framing error occurs. It must be cleared by software. Note that the

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 9-11Bit 0: Receive Interrupt Flag (RI). This bit indicates that a data byte has been received in the se

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 10-110.1 SPI Transfer Formats ...10-2

MAXQ612/MAXQ622 User’s Guide10-2 Maxim IntegratedSECTION 10: SERIAL PERIPHERAL INTERFACE (SPI) MODULEThe serial peripheral interface (SPI) module of

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-11Figure 2-5. CDA Functions in Byte ModeUTILITY ROMPHYSICAL DATAx0000x8000xA000xFFFFx0000x8000xFFFFDA

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 10-3transfer format. The polarity of the serial clock corresponds to the idle logic state of the clock

MAXQ612/MAXQ622 User’s Guide10-4 Maxim Integrated10.2 SPI Slave SelectThe SPI slave-select SSEL can be configured to accept either an active-low or a

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 10-5The application software must correct the system conflict before resuming its normal operation. The

MAXQ612/MAXQ622 User’s Guide10-6 Maxim Integratedthe first clock edge or the active SSEL edge, dependent on the data transfer format. When SAS is cle

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 10-7Bit 3: Mode Fault Flag (MODF). This bit is the mode fault flag for SPI master mode operation. When

MAXQ612/MAXQ622 User’s Guide10-8 Maxim Integrated10.8.3 SPI Clock Register (SPICKn)Bits 7:0: Clock Divider Ratio Bits 7:0 (CKR[7:0]). This 8-bit valu

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 11-111.1 I2C Mode of Operation...11-21

MAXQ612/MAXQ622 User’s Guide11-2 Maxim IntegratedSECTION 11: I2C INTERFACEThe MAXQ612/MAXQ622 provide an I2C module, which is an 8-bit, bidirectional

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 11-3flag is set (I2CTXI = 1). The I2CTXI flag is set after the acknowledge bit has been received from t

MAXQ612/MAXQ622 User’s Guide11-4 Maxim Integrated11.1.2 Master-ReceiverWhen operating in master mode with I2CMODE bit set to 1, the I2C module is ope

MAXQ612/MAXQ622 User’s Guide2-12 Maxim IntegratedFigure 2-6. CPA Impact on Code Pointer Access of Program Memory2.5.2 Memory Mapping into Code SpaceT

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 11-5The slave cannot write to the I2CBUF if a transfer is in progress (I2CBUSY = 1). Therefore, the CPU

MAXQ612/MAXQ622 User’s Guide11-6 Maxim Integrated11.1.4 Slave-ReceiverThe I2C module functions as a slave-receiver when an address match is identifie

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 11-7Similarly, if an external master pulls SCL low before the I2C controller has finished counting its

MAXQ612/MAXQ622 User’s Guide11-8 Maxim Integrated11.4 I2C Peripheral Register DescriptionsThe following peripheral registers are used to control the

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 11-9Bit 5: I2C Data Acknowledge Bit (I2CACK). This bit selects the acknowledge bit returned by the I2C

MAXQ612/MAXQ622 User’s Guide11-10 Maxim IntegratedBit 9: I2C Receiver Overrun Flag (I2CROI). This bit indicates a receive overrun when set to 1. This

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 11-1111.4.4 I2C Interrupt Enable Register (I2CIE)Bits 15 to 12 and 10: Reserved. Reads return 0.Bit 11:

MAXQ612/MAXQ622 User’s Guide11-12 Maxim Integrated11.4.5 I2C Clock Control Register (I2CCK)Bits 15 to 8: I2C Clock High (I2CCKH[7:0]). These bits def

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 11-1311.4.7 I2C Slave Address Register (I2CSLA)Bit 7: Reserved. Reads returns zero.Bits 6 to 0: I2C Sla

MAXQ612/MAXQ622 User’s Guide11-14 Maxim Integrated11.5.2 I2C Example: Master Mode, ReceiveI2C configured as master, receive from slave address 08h:;

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-13Figure 2-7. MAXQ622 Memory Map and UPAPHYSICAL DATAPHYSICAL DATAx0000x8000xFFFFx4000x4000DATA MEMOR

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 11-1511.5.4 I2C Example: Slave Mode, TransmitI2C configured as slave with address 1Ah:; Setup for Slave

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 12-112.1 USB SIE Endpoint Description...12-2

MAXQ612/MAXQ622 User’s Guide12-2 Maxim IntegratedSECTION 12: UNIVERSAL SERIAL BUS (USB) INTERFACENote: This section only applies to the MAXQ622.The M

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 12-312.2 USB SIE FeaturesThe hardware SIE does most of the signaling work required by the USB protocol,

MAXQ612/MAXQ622 User’s Guide12-4 Maxim IntegratedThis register is used to supply the offset location and control read/write access to the internal US

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 12-5Note: Writes to this register are ignored when UBUSY = 1.12.3.2 USB Data Register (UDATA)This regis

MAXQ612/MAXQ622 User’s Guide12-6 Maxim Integrated12.4.2 USB Control Register (USBCN)Bit 7: Oscillator Start (OSCST). Setting this bit to 1 allows the

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 12-712.4.4 USB Interrupt Enable Register (USBIEN)Note: This register is only accessible when USBEN = 1.

MAXQ612/MAXQ622 User’s Guide12-8 Maxim IntegratedBit 6: VBUS Detect (VBUS). This bit is set when the VBUSDET signal has made a 0-to-1 transition (VBU

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 12-9Bit 0: EP0-IN Buffer Available Interrupt Enable (IN0BAVIE). Setting this bit to 1 causes an interru

MAXQ612/MAXQ622 User’s Guide2-14 Maxim Integrated2.5.3 Memory Mapping RulesWhen executing program code in a particular memory segment, the same memor

MAXQ612/MAXQ622 User’s Guide12-10 Maxim Integrated12.4.8 Endpoint Stall Register (EPSTL)Bit 7: Reserved. Reads returns zero.Bit 6: Acknowledge Status

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 12-1112.4.9 Endpoint NAK Register (EPNAK)Bit 7: EP3-IN NAK (EP3NAK). The SIE sets this bit when the EP3

MAXQ612/MAXQ622 User’s Guide12-12 Maxim Integrated12.4.11 Endpoint 0 Byte Count Register (EP0BC)Bit 7: Reserved. Reads returns zero.Bits 6 to 0: EP0

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 12-1312.4.14 Endpoint 3 IN Byte Count Register (EP3BC)Bit 7: Reserved. Reads returns zero.Bits 6 to 0:

MAXQ612/MAXQ622 User’s Guide12-14 Maxim Integrated12.4.16 Endpoint 1 Buffer Register (EP1BUF)Note: This register is indetermistic on POR and retains

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 12-1512.4.18 Endpoint 3 Buffer Register (EP3BUF)Note: This register is indetermistic on POR and retains

MAXQ612/MAXQ622 User’s Guide12-16 Maxim Integrated12.5 USB Examples12.5.1 USB Example 1: Reading from an Internal USB Register (EPINT)To read from an

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 12-1712.5.2 USB Example 2: Writing to an Internal USB Register (EP2BC)To write to the USB state registe

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 13-113.1 TAP Controller ...13-21

MAXQ612/MAXQ622 User’s Guide13-2 Maxim IntegratedSECTION 13: TEST ACCESS PORT (TAP)The MAXQ612/MAXQ622 microcontrollers incorporate a test access por

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-152.5.4 Code ExamplesBecause the MAXQ622 uses the maximum allowed program flash supported by this cor

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 13-313.2.2 Run-Test-IdleAs illustrated in Figure 13-1, the run-test-idle state is simply an intermediat

MAXQ612/MAXQ622 User’s Guide13-4 Maxim IntegratedWhen the parallel instruction register (IR[2:0]) is updated, the TAP controller decodes the instruct

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 13-5Instruction register (IR[2:0]) settings other than those listed and described above are reserved fo

MAXQ612/MAXQ622 User’s Guide13-6 Maxim IntegratedFor the host to establish a specific data communication link, a private instruction must be loaded i

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 13-7Figure 13-4. TAP Controller Debug Mode DR-Scan ExampleOLD DATANEW DATADATA REGISTERTCKTMSTDITDOCONT

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 14-114.1 Background Mode Operation ...14-314

MAXQ612/MAXQ622 User’s Guide14-2 Maxim IntegratedSECTION 14: IN-CIRCUIT DEBUG MODEFlash-based MAXQ612/MAXQ622 microcontrollers are equipped with embe

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 14-3The host now can transmit and receive serial data through the 10-bit data shift register that exist

MAXQ612/MAXQ622 User’s Guide14-4 Maxim IntegratedTable 14-1. Background Mode CommandsOP CODE COMMAND OPERATION0000–0000 No Operation No operation (de

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 14-514.2 Breakpoint RegistersThe MAXQ612/MAXQ622 microcontrollers incorporate six breakpoint registers

MAXQ612/MAXQ622 User’s Guideii Maxim IntegratedTABLE OF CONTENTSSECTION 1: Overview ...

MAXQ612/MAXQ622 User’s Guide2-16 Maxim Integrated2.6 Memory ProtectionThe MAXQ612/MAXQ622 support privilege levels for code. When enabled, code memor

MAXQ612/MAXQ622 User’s Guide14-6 Maxim Integrateduser program. If an address match is detected, a break occurs, allowing the debug engine to take ove

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 14-714.3 Debug ModeThere are two ways to enter the debug mode from background mode:• Issuance of the d

MAXQ612/MAXQ622 User’s Guide14-8 Maxim Integratedreloading the debug instruction. Once the debug engine has received the proper number of command and

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 14-914.3.2 Read Register Map Command Host-Utility ROM InteractionA read register map command reads out

MAXQ612/MAXQ622 User’s Guide14-10 Maxim Integrated14.3.3 Single-Step Operation (Trace)The debug engine supports single step operation in debug mode b

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 14-11• Special caution should be exercised when using the write register command on regis

MAXQ612/MAXQ622 User’s Guide14-12 Maxim IntegratedBit 5: Break-On Register Enable (REGE). The REGE bit is used to enable the break on register functi

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 14-1314.4.4 In-Circuit Debug Buffer Register (ICDB)This register serves as the parallel holding buffer

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 15-115.1 JTAG Bootloader Operation...15-21

MAXQ612/MAXQ622 User’s Guide15-2 Maxim IntegratedSECTION 15: IN-SYSTEM PROGRAMMING (JTAG)Internal nonvolatile (flash) memory of MAXQ612/MAXQ622 micro

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-17This means that when using PRIVT0/PRIVT1, the privilege level cannot be raised unless all code betw

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 15-315.2 Password-Protected AccessSome applications require preventive measures to protect against simp

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-1SECTION 16: MAXQ612/MAXQ622 INSTRUCTION SET SUMMARYTable 16-1. MAXQ612/MAXQ622 Instruction Set Summ

MAXQ612/MAXQ622 User’s Guide16-2 Maxim IntegratedTable 16-1. MAXQ612/MAXQ622 Instruction Set Summary (continued)Note 1: The active accumulator (Acc)

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-3ADD/ADDC src Add/Add with CarryDescription:The ADD instruction sums the active accumulator (Acc or

MAXQ612/MAXQ622 User’s Guide16-4 Maxim IntegratedAND src Logical ANDDescription:Performs a logical-AND between the active accumulator (Acc) and the s

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-5{L/S}CALL src {Long/Short} Call to SubroutineDescription:Performs a call to the subroutine destinat

MAXQ612/MAXQ622 User’s Guide16-6 Maxim IntegratedCMP src Compare AccumulatorDescription:Compare for equality between the active accumulator and the l

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-7Encoding:150f10n1101 ssss ssssExample(s):MOVE LC[1], #10h ; counter = 10hLoop:ADD @DP[0]++ ; add da

MAXQ612/MAXQ622 User’s Guide16-8 Maxim Integrated{L/S} JUMP C/{L/S} JUMP NC, src {L/S} JUMP Z/{L/S} JUMP NZ, src{L/S} JUMP E/{L/S} JUMP NE, src{L/S}

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-9JUMP EOperation:E=1: IP ← IP + src (relative) –or— src (absolute)E=0: IP ← IP + 1Encoding:150001111

MAXQ612/MAXQ622 User’s Guide2-18 Maxim Integrated• A system library function that checks arguments before raising the privilege level must do so in

MAXQ612/MAXQ622 User’s Guide16-10 Maxim IntegratedTable 16-2. Source Specifier Codessrcsrc BIT ENCODINGf ssssssssWIDTH16 OR 8DESCRIPTION#k 0 kkkk kkk

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-11Table 16-3. Destination Specifier Codesdstdst BIT ENCODINGddd ddddWIDTH16 OR 8DESCRIPTIONNUL 111 0

MAXQ612/MAXQ622 User’s Guide16-12 Maxim IntegratedData Transfer Rulesdst (16-bit) ← src (16-bit): dst[15:0] ← src[15:0]dst (8-bit) ← src (8-bit): dst

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-13MOVE C, src.<b> Move Bit to Carry FlagDescription:Replaces the Carry (C) status flag with th

MAXQ612/MAXQ622 User’s Guide16-14 Maxim IntegratedMOVE dst.<b>, #1 Set BitDescription:Sets the bit specified by dst.<b>.Status Flags:C, E

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-15OR Acc.<b> Logical OR Carry Flag with Accumulator BitDescription:Performs a logical-OR betwe

MAXQ612/MAXQ622 User’s Guide16-16 Maxim IntegratedPUSH src Push Word to the StackDescription:Increases the stack depth (decments the stack pointer SP

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-17RET C/RET NC RET Z/RET NZRET SConditional Return on Status FlagDescription:Performs conditional re

MAXQ612/MAXQ622 User’s Guide16-18 Maxim IntegratedRET SOperation:S=1: IP ← @SP--S=0: IP ← IP + 1Encoding:1501100 1100 0000 1101Example(s):RET S ; S=0

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-19RETI NCOperation:C=0: IP ← @SP--IPS ← 11bC=1: IP ← IP +1Encoding:1501110 1100 1000 1101Example(s):

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-19This is no different for instructions that operate on data pointers. For example, a pointer to poin

MAXQ612/MAXQ622 User’s Guide16-20 Maxim IntegratedRL/RLCRotate Left Accumulator Carry Flag Exclusive/InclusiveDescription:Rotates the active accumula

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-21RR/RRCRotate Right Accumulator Carry Flag Exclusive/InclusiveDescription:Rotates the active accumu

MAXQ612/MAXQ622 User’s Guide16-22 Maxim IntegratedSLA/SLA2/SLA4Shift Accumulator Left Arithmetically One, Two, or Four TimesDescription:Shifts the ac

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-23SR SRA/SRA2/SRA4Shift Accumulator Right Shift Accumulator Right Arithmetically One, Two, or Four T

MAXQ612/MAXQ622 User’s Guide16-24 Maxim IntegratedSRA4 Operation:15 Active Accumulator (Acc) 0 Carry Flag→ → →Acc.[11:0] ← Acc.[15:4]Acc.[15:12] ← Ac

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 16-25XCHExchange Accumulator BytesDescription:Exchanges the upper and lower bytes of the active accumul

MAXQ612/MAXQ622 User’s Guide16-26 Maxim IntegratedXOR Acc.<b> Logical XOR Carry Flag with Accumulator BitDescription:Performs a logical-XOR bet

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 17-117.1 In-Application Programming Functions ...17

MAXQ612/MAXQ622 User’s Guide17-2 Maxim IntegratedSECTION 17: UTILITY ROMThe MAXQ612/MAXQ622 utility ROM includes routines that provide the following

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 17-317.1 In-Application Programming Functions17.1.1 UROM_flashWriteNotes:• This function uses one stac

MAXQ612/MAXQ622 User’s Guide2-20 Maxim IntegratedNext, the RAM routine calls into the flash function. Once we are executing out of flash, we can acti

MAXQ612/MAXQ622 User’s Guide17-4 Maxim Integrated17.2 Data Transfer Functions17.2.1 UROM_moveDP0Notes:• Before calling this function, DPC should be

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 17-517.2.4 UROM_moveDP1Notes:• Before calling this function, DPC should be set appropriately to config

MAXQ612/MAXQ622 User’s Guide17-6 Maxim Integrated17.2.7 UROM_moveFPNotes:• Before calling this function, DPC should be set appropriately to configur

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 17-717.2.10 UROM_moveBPNotes:• Before calling this function, DPC should be set appropriately to config

MAXQ612/MAXQ622 User’s Guide17-8 Maxim Integrated17.4 ROM Example 1: Calling A Utility ROM Function DirectlyThis example shows the direct addressing

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 17-917.5 ROM Example 2: Calling A Utility ROM Function IndirectlyThe second example shows the indirect

Maxim Integrated A1-1MAXQ612/MAXQ622 User’s GuideAPPENDIX 1: DATA POINTER USAGE EXAMPLESIMPORTANT: MAXQ20 family pointer mode (DPC.WBS) bits and so

A1-2 Maxim IntegratedMAXQ612/MAXQ622 User’s Guide; execute function code here;move DPC, #4 ; restore thepop DP[0] ; word mode version of DP[0]move DP

Maxim Integrated A1-3MAXQ612/MAXQ622 User’s GuidePointer deactivationAny time a pointer is activated another is deactivated.1) Writing addresses to

A1-4 Maxim IntegratedMAXQ612/MAXQ622 User’s Guidemove ACC, @DP[1] ; DP[1] is now properly configured properly to read********************************

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-21Figure 2-8 shows the code memory with passwords and the location of the values that are programmed

Maxim Integrated A1-5MAXQ612/MAXQ622 User’s Guidemove DP[1], DP[1] ; select DP[1] as the active source pointer by; writing to the pointer registermo

A1-6 Maxim IntegratedMAXQ612/MAXQ622 User’s Guidemove DPC, ACC ; write the new mode valuepush DP[1] ; save byte mode bitsmove DP[1], DP[1] ; select D

Maxim Integrated A1-7MAXQ612/MAXQ622 User’s Guide; pointer as the active source.move ACC, @DP[1] ; *WRONG* DP[1] is *NOT* properly configured proper

MAXQ612/MAXQ622 User’s GuideMaxim Integrated I-1INDEXCclock 2-23, 2-25, 3-18, 3-19, 3-20, 6-2, 6-3, 7-2, 7-4, 7-8, 7-9, 8-2, 8-4, 8-5, 8-6, 8-10, 9-

MAXQ612/MAXQ622 User’s GuideI-2 Maxim IntegratedSSIE 12-3SPI 1-2, 2-3, 2-31, 2-32, 6-2, 6-3, 10-2, 10-3, 10-4, 10-5, 10-6, 10-7, 10-8, 16-2, 16-10SPI

MAXQ612/MAXQ622 User’s Guide Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxi

MAXQ612/MAXQ622 User’s Guide2-22 Maxim Integrated2.6.7 Loader Access ControlAs stated previously, the MAXQ612/MAXQ622 have three memory regions: syst

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-232.6.8 Disabling MAXQ612/MAXQ622-Specific Memory Access FeaturesThe MAXQ612/MAXQ622 memory-protectio

MAXQ612/MAXQ622 User’s Guide2-24 Maxim IntegratedFigure 2-9. MAXQ612/MAXQ622 Clock SourcesFigure 2-10. On-Chip Crystal OscillatorGLITCH-FREEMUXDIV 1D

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-25Crystal specifications, operating temperature, operating voltage, and parasitic capacitance must be

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 1-1SECTION 1: OVERVIEWThe MAXQM family of 16-bit reduced instruction set computing (RISC) microcontroll

MAXQ612/MAXQ622 User’s Guide2-26 Maxim Integrated2.8.1 Using the Wake-Up Timer to Exit Stop ModeTo use the wake-up timer to exit stop mode after a pr

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-272) The IPS bits are set to 11b to re-enable interrupt handling.3) The instruction pointer is set

MAXQ612/MAXQ622 User’s Guide2-28 Maxim IntegratedTable 2-8. Interrupt Priority*With the exception of the power-fail interrupt, all interrupts require

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-29Table 2-9. Power-Fail Reset Check Interval2.9.5 Interrupt Exception WindowAn interrupt exception wi

MAXQ612/MAXQ622 User’s Guide2-30 Maxim IntegratedThe MAXQ612/MAXQ622 support power-fail detection where an on-chip bandgap and reference comparator c

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-312.11.3 Watchdog Timer ResetThe watchdog timer is a programmable hardware timer that can be set to r

MAXQ612/MAXQ622 User’s Guide2-32 Maxim IntegratedIf switchback is enabled, a processor running under power-management mode automatically clears the P

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 3-13.1 Addressing Modes...3-33.2

MAXQ612/MAXQ622 User’s Guide3-2 Maxim IntegratedLIST OF FIGURESFigure 3-1. Watchdog Timer Block Diagram ...

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 3-3SECTION 3: PROGRAMMINGThis section provides a programming overview of the MAXQ612/MAXQ622. For full

MAXQ612/MAXQ622 User’s Guide1-2 Maxim IntegratedPeripheral registers (module 0 to module 5) on the MAXQ612/MAXQ622 contain registers that are used to

MAXQ612/MAXQ622 User’s Guide3-4 Maxim IntegratedHowever, the operation:move DP[0], #0055hdoes not require a prefixing operation even though the regi

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 3-53.3.4 Moving Values Between Registers of Different SizesBefore covering some transfer scenarios that

MAXQ612/MAXQ622 User’s Guide3-6 Maxim Integrated3.3.8 Low (16-Bit Destination) ← 8-Bit SourceTo modify only the low byte of a given 16-bit destinatio

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 3-7Register bits can be set or cleared individually using the MOVE instruction as follows:move IGE, #1

MAXQ612/MAXQ622 User’s Guide3-8 Maxim Integrated• SRA4 (Arithmetic shift right active accumulator 4 bit positions)• RL (Rotate active accu

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 3-9• Increment modulo 8: AP = AP[3] + ((AP[2:0] + 1) mod 8)• Decrement modulo 8: AP = AP[3] + ((AP[

MAXQ612/MAXQ622 User’s Guide3-10 Maxim Integratedsra ; Shift accumulator right arithmetically oncesra2 ; Shift accumulator right arithmet

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 3-113.6.2 Zero FlagThe zero flag (PSF.7) is a dynamic flag that reflects the current state of the activ

MAXQ612/MAXQ622 User’s Guide3-12 Maxim Integrated• MOVE Acc.<b>, C (Set selected active accumulator bit to carry)• AND Acc.<b> (Carr

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 3-133.7.3 Conditional JumpsConditional jumps transfer program execution based on the value of one of th

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-1SECTION 2: ARCHITECTURE2.1 Instruction Decoding ...

MAXQ612/MAXQ622 User’s Guide3-14 Maxim IntegratedWhen the supplied loop address is outside the relative jump range, the prefix register (PFX[0]) is u

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 3-153.7.7 Conditional Return from InterruptSimilar to the conditional returns, the MAXQ612/MAXQ622 micr

MAXQ612/MAXQ622 User’s Guide3-16 Maxim IntegratedBecause the stack is 16 bits wide, it is possible to store two 8-bit register values on it in a sing

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 3-17the current WBSn selection. Data pointer increment and decrement operations only affect those bits

MAXQ612/MAXQ622 User’s Guide3-18 Maxim Integratedmove @--DP[1], @DP[1]--move @BP[--Offs], @BP[Offs--]move @++DP[0], @DP[0]--move @++DP[1], @DP[1]--mo

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 3-19the watchdog timer is reset (RWT bit written to 1) before the timeout period expires, the timer sta

MAXQ612/MAXQ622 User’s Guide3-20 Maxim Integratedthe processor to the lost position prior to the interrupt. By using the watchdog reset function, the

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 4-14.1 System Register Descriptions ...4-5

MAXQ612/MAXQ622 User’s Guide4-2 Maxim IntegratedSECTION 4: SYSTEM REGISTER DESCRIPTIONRegisters currently defined in the MAXQ612/MAXQ622 system regis

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 4-3Table 4-2. System Register Bit MapREGBIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0AP — — — — AP (4 bits)A

MAXQ612/MAXQ622 User’s Guide2-2 Maxim IntegratedLIST OF FIGURESFigure 2-1. MAXQ612/MAXQ622 Transport-Triggered Architecture ...

MAXQ612/MAXQ622 User’s Guide4-4 Maxim IntegratedTable 4-3. System Register Bit Reset ValuesNote 1: Bits marked as “s” are static across some or all r

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 4-54.1 System Register DescriptionsThe addresses for each register are given in the format module[index

MAXQ612/MAXQ622 User’s Guide4-6 Maxim IntegratedREGISTER DESCRIPTIONPRIV, 08h[02h]Privilege Register (8 bits)Initialization This register is reset to

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 4-7REGISTER DESCRIPTIONPSF, 08h[04h]Processor Status Flags Register (8 bits)Initialization This registe

MAXQ612/MAXQ622 User’s Guide4-8 Maxim IntegratedREGISTER DESCRIPTIONIC, 8h[5h]Interrupt and Control Register (8 bits)Initialization This register is

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 4-9REGISTER DESCRIPTIONSC, 08h[08h]System Control Register (16 bits)Initialization This register is res

MAXQ612/MAXQ622 User’s Guide4-10 Maxim IntegratedREGISTER DESCRIPTIONSC.9 (PWLL) Password Lock User Loader. This bit defaults to 1 on power-fail and

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 4-11REGISTER DESCRIPTIONIPR1, 08h[0Ah]Interrupt Priority Register One (16 bits)Initialization This regi

MAXQ612/MAXQ622 User’s Guide4-12 Maxim IntegratedREGISTER DESCRIPTIONULDR, 08h[0Ch]User Loader Starting Page Address (16 bits)Initialization This reg

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 4-13REGISTER DESCRIPTIONWDCN, 08h[0Fh]Watchdog Control Register (8 bits)Initialization Bits 5, 4, 3, an

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-3SECTION 2: ARCHITECTUREThe MAXQ612/MAXQ622 are designed to be modular and expandable. Top-level inst

MAXQ612/MAXQ622 User’s Guide4-14 Maxim IntegratedREGISTER DESCRIPTIONWDCN.6 (EWDI) Watchdog Interrupt Enable. If this bit is set to 1, an interrupt r

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 4-15REGISTER DESCRIPTIONIP, 0Ch[00h]Instruction Pointer Register (16 bits)Initialization This register

MAXQ612/MAXQ622 User’s Guide4-16 Maxim IntegratedREGISTER DESCRIPTIONDPC, 0Eh[04h]Data Pointer Control Register (16 bits)Initialization This register

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 4-17REGISTER DESCRIPTIONGRS, 0Eh[08h]General Register Byte-Swapped (16 bits)Initialization This registe

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-15.1 Peripheral Register Bit Descriptions ...

MAXQ612/MAXQ622 User’s Guide5-2 Maxim IntegratedSECTION 5: PERIPHERAL REGISTER MODULESThe MAXQ612/MAXQ622 microcontroller uses peripheral registers t

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-3Table 5-2. Peripheral Register Bit Function (continued)REGBIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0CH

MAXQ612/MAXQ622 User’s Guide5-4 Maxim IntegratedTable 5-3. Peripheral Register Reset ValuesTable 5-2. Peripheral Register Bit Function (continued)REG

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-5Table 5-3. Peripheral Register Reset Values (continued)REGBIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0TB

MAXQ612/MAXQ622 User’s Guide5-6 Maxim Integrated5.1 Peripheral Register Bit DescriptionsREGISTER DESCRIPTIONPO0 (00h, 00h) Port 0 Output Register (8-

MAXQ612/MAXQ622 User’s Guide2-4 Maxim IntegratedMemory access from the MAXQ612/MAXQ622 is based on a Harvard architecture with separate address space

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-7REGISTER DESCRIPTIONEIF1 (06h, 00h) External Interrupt Flag 1 RegisterInitialization: EIF1 is cleare

MAXQ612/MAXQ622 User’s Guide5-8 Maxim IntegratedREGISTER DESCRIPTIONPI3 (0Bh, 00h) Port 3 Input RegisterInitialization: The reset value for this regi

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-9REGISTER DESCRIPTIONPD2 (12h, 00h) Port 2 Direction RegisterInitialization: This register is cleared

MAXQ612/MAXQ622 User’s Guide5-10 Maxim IntegratedREGISTER DESCRIPTIONPO6 (02h, 01h) Port 6 Output Register (8-bit register)Initialization: This regis

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-11REGISTER DESCRIPTIONPI4 (08h, 01h) Port 4 Input RegisterInitialization: The reset value for this re

MAXQ612/MAXQ622 User’s Guide5-12 Maxim IntegratedREGISTER DESCRIPTIONPWCN.4 (IRTXOE) IRTX Output Enable. The IRTXOE bit is used in conjunction with t

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-13REGISTER DESCRIPTIONPWCN.12 (CTM) Crystal Multiplier Enable. The CTM bit is used to enable the crys

MAXQ612/MAXQ622 User’s Guide5-14 Maxim IntegratedREGISTER DESCRIPTIONTB0R (00h, 02h) Timer B0 Capture/Reload Value Register (16-bit register)Initiali

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-15REGISTER DESCRIPTIONTB0CN.5 (TBOE) Timer B Output Enable. Setting this bit to 1 enables the clock o

MAXQ612/MAXQ622 User’s Guide5-16 Maxim IntegratedREGISTER DESCRIPTIONIRCN (04h, 02h) Infrared Control Register (16-bit register)Initialization: This

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 2-5The MAXQ instruction set is designed to be highly orthogonal. All arithmetic and logical operations

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-17REGISTER DESCRIPTIONIRCN.12 to IRCN.10 (IRDIV[2:0]) IR Clock Divide Bits. These two bits select the

MAXQ612/MAXQ622 User’s Guide5-18 Maxim IntegratedREGISTER DESCRIPTIONTB0C (08h, 02h) Timer B0 Compare Register (16-bit register)Initialization: This

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-19REGISTER DESCRIPTIONSCON0.6 (SM1)SCON0.7 (SM0/FE)Serial Port 0 Mode Bits 1:0 (when FEDE is 0). When

MAXQ612/MAXQ622 User’s Guide5-20 Maxim IntegratedREGISTER DESCRIPTIONSCON1 (02h, 03h) Serial Port 1 Control Register Initialization: The serial port

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-21REGISTER DESCRIPTIONSBUF1 (03h, 03h) Serial Data Buffer 1Initialization: This buffer is cleared to

MAXQ612/MAXQ622 User’s Guide5-22 Maxim IntegratedREGISTER DESCRIPTIONSPICN1 (07h, 03h) SPI Control Register 1Initialization: This buffer is cleared t

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-23REGISTER DESCRIPTIONPR1 (0Ah, 03h) Phase Register 1Initialization: The phase register is cleared to

MAXQ612/MAXQ622 User’s Guide5-24 Maxim IntegratedREGISTER DESCRIPTIONSPICF1 (0Eh, 03h) SPI Configuration Register 1Initialization: This buffer is cle

MAXQ612/MAXQ622 User’s GuideMaxim Integrated 5-25REGISTER DESCRIPTIONI2CCN.3:Reserved. Read returns 0.I2CCN.4 (I2CSTRS) I2C Clock Stretch Select. Se

MAXQ612/MAXQ622 User’s Guide5-26 Maxim IntegratedREGISTER DESCRIPTIONI2CST (01h, 04h) I2C Status Register (16-bit register)Initialization: This regis