Maxim-integrated MAXQ622 Bedienungsanleitung PDF herunterladen (Seite 97)

MAXQ612/MAXQ622 User’s Guide

5-24 Maxim Integrated

SPICF1 (0Eh, 03h) SPI Configuration Register 1

Initialization: This buffer is cleared to 00h on all forms of reset.

Read/Write Access: Unrestricted read/write.

SPICF1.0 (CKPOL) Clock Polarity Select. This bit is used with the CKPHA bit to determine the SPI transfer

format. When the CKPOL is set to 1, the SPI uses the clock falling edge as an active edge.

When the CKPOL is cleared to 0, the SPI selects the clock rising edge as an active edge.

SPICF1.1 (CKPHA) Clock Phase Select. This bit is used with the CKPOL bit to determine the SPI transfer

format. When the CKPHA is set to 1, the SPI samples input data at an inactive edge. When

the CKPHA is cleared to 0, the SPI samples input data at an active edge.

SPICF1.2 (CHR) Character Length Bit. The CHR bit determines the character length for an SPI transfer

cycle. A character can consist 8 or 16 bits in length. When CHR bit is 0, the character is 8

bits; when CHR is set to 1, the character is 16 bits.

SPICF1.5 to SPICF1.3 Reserved. Reads return 0.

SPICF1.6 (SAS)

Slave Active Select. This bit is used to determine the SSEL active state. When the SAS is

cleared to 0, the SSEL is active low and responds to an external low signal. When the SAS

is set to 1, the SSEL is active high.

SPICF1.7 (ESPII) SPI Interrupt Enable. Setting this bit to 1 enables the SPI interrupt when MODF, WCOL,

ROVR, or SPIC flags are set. Clearing this bit to 0 disables the SPI interrupt.

SPICK1 (0Fh, 03h) SPI Clock Register 1

Initialization: This buffer is cleared to 00h on all forms of reset.

Read/Write Access: Unrestricted read/write.

SPICK1.7 to SPICK1.0 (CKR[7:0]) Clock-Divide Ratio Bits 7:0. These bits select one of the 256 divide ratios (0 to 255) used

for the baud-rate generator, with bit 7 as the most significant bit. The frequency of the SPI

baud rate is calculated using the following equation:

SPI Baud Rate = 0.5 x System Clock/(divide ratio + 1)

This register has no function when operating in slave mode and the clock generation

circuitry should be disabled.

I2CCN (00h, 04h) I

C Control Register (16-bit register)

Initialization: This register is cleared to 0000h on all forms of reset. The I2CSTART and I2CSTOP bits are

reset to 0 when I2CMST = 0 or when I2CEN = 0. I2CSTART and I2CSTOP are a mutually

exclusive operation. User software can only set one of these bits at any given time. I2CRST

is reset to 0 when I2CEN = 0.

Read/Write Access: Unrestricted read. Unrestricted write access when I2CBUSY = 0. Writes to I2CMST and

I2CMODE are ignored when I2CBUSY = 1. Writes to I2CEN are normally disabled when

I2CBUSY = 1. However, when the I2CRST = 1, I2CEN can be written to even when

I2CBUSY = 1. Writes to I2CACK are ignored when I2CRST = 1.

I2CCN.0 (I2CEN) I

C Enable. This bit enables the I

C function. When set to 1, the I

C communication unit is

enabled. When cleared to 0, the I

C function is disabled.

I2CCN.1 (I2CMST) I

C Master Mode Enable. The I2CMST bit functions as a master mode-enable bit for the

C module. When the I2CMST bit is set to 1, the I

C operates as a master. When the

I2CMST is cleared to 0, the I

C module operates in slave mode. This bit is automatically

cleared whenever the I

C controller receives a slave address match (I2CAMI = 1), loses

arbitration (I2CALI = 1), or through a general call (I2CGCI = 1).

I2CCN.2 (I2CMODE) I

C Transfer Mode. The transfer mode bit selects the direction of data transfer with respect

to the master. When the I2CMODE bit is set to 1, the master is operating in receiver mode

(reading from slave). When the I2CMODE bit is cleared to 0, the master is operating in

transmitter mode (writing to slave). Note that software writing to this bit is prohibited in slave

mode. When operating in master mode, software configures this bit to the desired direction

of data transfer. When operating in slave mode, the direction of data transfer is determined

by the R/W bit received during the address stage and this bit reflects the actual R/W bit

value in the current transfer and is set by hardware. Software writing to this bit in slave

mode is ignored.

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