MAXQ612/MAXQ622 User’s Guide
2-32 Maxim Integrated
If switchback is enabled, a processor running under power-management mode automatically clears the PMME bit to
0 and returns to normal mode when any of the following conditions occur:
• An external interrupt condition occurs on an INTn pin and the corresponding external interrupt is enabled.
• An active-low transition occurs on the USART serial receive input line (modes 1, 2, and 3) and data reception is
enabled.
• The SBUF register is written to send an outgoing byte through the USART and transmission is enabled.
• The SPIB register is written in master mode (STBY = 1) to send an outgoing character through the SPI module and
transmission is enabled.
• The SPI module’s SSEL signal is asserted in slave mode.
• Active debug mode is entered either by breakpoint match or issuance of the debug command from background
mode.
• Power-fail interrupt if enabled (PFIE = 1).
2.13 Stop Mode
When the MAXQ612/MAXQ622 are in stop mode, the CPU system clock is stopped and all processing activity is halted.
All on-chip peripherals requiring the system clock are also stopped. Power consumption in the lowest power stop mode
is basically limited to static leakage current.
Stop mode is entered by setting the STOP bit to 1. The processor enters stop mode immediately once the instruction
that sets the STOP bit is executed.
Note: It is necessary to include a ‘nop’ immediately following the instruction to invoke stop mode for proper interrupt
operation. Example code is as follows:
move ckcn, #010h ; enter stop mode
nop ; No operation to cause a one cycle delay
The MAXQ612/MAXQ622 exit stop mode when any of the following conditions occur:
• An external interrupt condition occurs on one of the INTn pins and the corresponding external interrupt is enabled.
After the interrupt returns, execution resumes after the stop point.
• An external reset signal is applied to the RESET pin. After the reset signal is removed, execution resumes from utility
ROM at 8000h as it would after any reset state.
• A power-fail interrupt occurs, if enabled (PFIE = 1).
• A wake-up timer interrupt occurs, if enabled (WTE = 1).
Note that the voltage monitor and bandgap reference can be disabled during stop mode to conserve current con-
sumption. In this case, a power-fail condition does not cause a reset as it would under normal conditions. However,
the POR monitor remains enabled, and any voltage drop on V
DD
that goes below the POR level causes a POR to
occur. To continue to monitor supply voltage during stop mode, the power-fail monitor is left on if the regulator is left
on (REGEN = 1), or it can be explicitly enabled (if the regulator is disabled; REGEN = 0) by clearing the PWCN.PFD bit
to 0. The power-fail monitor is always enabled prior to stop mode exit and resumption of code execution.
Once the processor exits stop mode, it resumes execution as follows:
• If the crystal oscillator is selected as the system clock source, the crystal oscillator is started and execution resumes
following an 8192-clock-cycle delay to allow the oscillator frequency to stabilize.
(93 Seiten)
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