Maxim-integrated MAXQ622 Bedienungsanleitung PDF herunterladen (Seite 98)

MAXQ612/MAXQ622 User’s Guide

Maxim Integrated 5-25

I2CCN.3:

Reserved. Read returns 0.

I2CCN.4 (I2CSTRS) I

C Clock Stretch Select. Setting this bit to 1 enables clock stretching after the falling edge of

the 8th clock cycle. Clearing this bit to 0 enables clock stretching after the falling edge of the

9th clock cycle. This bit has no effect when clock stretching is disabled (I2CSTREN = 0).

I2CCN.5 (I2CACK) I

C Data Acknowledge Bit. This bit selects the acknowledge bit returned by the I

controller while acting as a receiver. Setting this bit to 1 generates a NACK (leaving SDA

high). Clearing the I2CACK bit to 0 generates an ACK (pulling SDA LOW) during the

acknowledgement cycle. This bit retains its value unless changed by software or hardware.

When an I

C abort is in progress (I2CRST = 1), this bit is set to 1 by hardware and software

and writes to this bit are ignored when I2CRST = 1.

I2CCN.6 (I2CSTART) I

C START Enable. Setting this bit automatically generates a START condition when

the bus is free or a repeated START condition during a transfer where the I

C module is

operating as the master. This bit automatically is self-cleared to 0 after the START condition

has been generated. If the I

C START interrupt is enabled, a START condition generates an

interrupt to the CPU.

In master mode, setting this bit may also start the timeout timer if enabled. If the timeout

timer expires before the START condition can be generated, a timeout interrupt will be

generated to the CPU if enabled. The I2CSTART bit will also be cleared to ‘0’ by the

timeout event.

Note that this bit has no effect when the I2C is operating in slave mode (I2CMST=0) and will

be reset to ‘0’ when I2CMST =0 or I2CEN=0. Also the I2CSTART and I2CSTOP are mutually

exclusive. If both bits are set at the same time, it is considered as an invalid operation and

the I2C controller will ignore the request and reset both bits to 0. Setting the I2CSTART bit

to 1 while I2CSTOP = 1 is an invalid operation and will be ignored, leaving I2CSTART bit

cleared to 0.

I2CCN.7 (I2CSTOP) I

C STOP Enable. Setting this bit to 1 generates a STOP condition. This bit is automatically

self-cleared to 0 after the STOP condition has been generated.

In master mode, setting this bit may also start the timeout timer if enabled. If the timeout

timer expires before the STOP condition can be generated, a timeout interrupt will be

generated to the CPU if enabled. The I2CSTOP bit will also be cleared to ‘0’ by the timeout

event.

Note that this bit has no effect when the I2C is operating in slave mode (I2CMST=0) and will

be reset to ‘0’ when I2CMST=0 or I2CEN=0. Setting the I2CSTOP bit to 1 while I2CSTART =

1 is an invalid operation and will be ignored, leaving I2CSTOP bit cleared to 0.

I2CCN.8 (I2CGCEN) I

C General Call Enable. Setting this bit to 1 enables the I

C to respond to a general

call address (address = 0000 0000). Clearing this bit to 0 disables the I

C to respond to

general call address.

I2CCN.9 (I2CSTREN) I

C Clock Stretch Enable. Setting this bit to 1 stretches the clock (hold SCL low) at the end

of the clock cycle specified in I2CSTRS. Clearing this bit disables clock stretching.

I2CCN.14:10

Reserved. Read returns 0.

I2CCN.15 (I2CRST) I

C Reset. Setting this bit to 1 aborts the current transaction and resets the I

C controller.

This bit is set to 1 by software and is only cleared to 0 by hardware after the reset or when

I2CEN = 0.

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