Maxim-integrated MAXQ7667 Bedienungsanleitung PDF herunterladen (Seite 138)

8.3.5 Error Register (UART) (ERRR)

egister Name:

RRR

Bit 7: Reserved.

Read returns 0.

Bit 6: Other Communications Error (OTE). This bit is set to 1 by the peripheral whenever a communication error occurs that is not

covered by one of the other error flags.

Bit 5: Data Mismatch Error (DME). This bit is set to 1 by the peripheral when a transmitted byte is not read back correctly.

Bit 4: Checksum Error (CKE). This bit is set to 1 by the peripheral when a received checksum does not match the calculated check-

sum for that frame.

Bit 3: Parity Bit 1 (P1). This bit reflects the status of the P1 parity bit for the most recently received frame. It is updated by the periph-

eral every time a header is received.

Bit 2: Parity Bit 1 Error (P1E). This bit is set to 1 by the peripheral whenever a header is received with an error in the P1 parity bit. It

is cleared to 0 by the peripheral when a header is received with the correct value in the P1 parity bit.

Bit 1: Parity Bit 0 (P0). This bit reflects the status of the P0 parity bit for the most recently received frame. It is updated by the periph-

eral every time a header is received.

Bit 0: Parity Bit 0 Error (P0E). This bit is set to 1 by the peripheral whenever a header is received with an error in the P0 parity bit. It

is cleared to 0 by the peripheral when a header is received with the correct value in the P0 parity bit.

___________________________________________________________________________________________________________ 8-8

MAXQ7667 User’s Guide

r = read

Note: ERRR is cleared to 00h on all forms of reset.

Bit #

76543210

Name — OTE DME CKE P1 P1E P0 P0E

Reset 0 0 0 0 0 0 0 0

Access r r rrrrrr

1 2 ... 133 134 135 136 137 138 139 140 141 142 143 ... 346 347

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Maxim-integrated MAXQ7667 Bedienungsanleitung Seite 138