_________________________________________________________________________________________________________ 19-14
dst
dst BIT EN COD ING
(d d d d d dd )
WI DT H
(16 OR 8)
DESCRIPTION
N UL 111 0110 8/16
Null (V i rtual) Destination. Intended as a bit bucket to ass ist
software with pointer increments/decrements.
MN[n] nnn 0NNN 8/16
nnnn Selects One of Firs t 8 Registers in Module NNN; where
N N N = 0 to 5. Access to Next 24 U sing PFX[n].
AP 000 1000 8 Accumulator Pointer
APC 001 1000 8 Accumulator Pointer Control
PSF 100 1000 8 Processor Status Flag Register
IC 101 1000 8 Inter rupt and Control Register
IMR 110 1000 8 Inter rupt Mask Register
A[n] nnn 1001 8/16 nnn Selects 1 of Firs t 8 Accumulators: A[0]..A[7]
Acc 000 1010 8/16 Active Accumulator = A[AP ]
PFX[n] nnn 1011 8 nnn Selects One of 8 Prefix Registers
@++SP 000 1101 16 16-Bit Word @SP, Pre-Increment SP
SP 001 1101 16 Stack Pointer
IV 010 1101 16 Interrupt Vector
LC[n] 11n 1101 16 n Selects 1 of 2 Loop Counter Registers
@BP[OFFS] 000 1110 8/16 Data Memory @BP[OFFS]
@BP[++OFFS] 001 1110 8/16 Data Memory @BP[OFFS]; P reincrement OFFS
@BP[ - -OFFS ] 010 1110 8/16 Data Me mory @BP[OFFS]; Predecrement OFFS
OFFS 011 1110 8 Frame Pointer Offset from Base Pointer (BP)
D P C 100 1110 16 Data Pointer C ontrol Register
GR 101 1110 16 General Register
GRL 110 1110 8 Low Byte of GR Regis ter
BP 111 1110 16 Frame Pointer Base Pointer (BP )
@DP[n] n00 1111 8/16 Data Memory @DP[n ]
@++DP[n] n01 1111 8/16 Data Memory @DP [n ], Preincrement DP [n ]
@-- D P [n] n10 1111 8/16 Data Memory @DP[n ], Predecrement DP [n]
D P [n] n11 1111 16 n Selects 1 of 2 Data Pointers
2- C YC LE DESTINATION AC CESS U SING PFX[n] REGISTER (See Special No tes)
SC 000 1000 8 System C ontrol Register
CKC N 110 1000 8 Clock Control Register
WDCN 111 1000 8 Watchdog C ontrol Register
A[n] nnn 1001 16 nnn Selects 1 of Second 8 Accumulators A[8]…A[15]
GRH 001 1110 8 Hi gh Byte of GR Register
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