Maxim-integrated MAXQ7667 Bedienungsanleitung PDF herunterladen (Seite 214)

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MAXQ7667 User’s Guide

Table 12-2. Background Mode Debug Commands

OP CODE C O MM A N D OPERATION

0010-0000 N o O peration N o Operation

0010-0001 Read Register Map

Read D ata from Internal Registers. This command forces the debug engine to update the C M D [3:0] b its in the

ICD C to 0001b and perform a jump to ROM code at 8010h. The ROM debug service routine wi ll load register data to

ICDB for host capture/read, starting at the lowest register location in module 0, one byte at a ti me in a success ive

order until all internal registers are read and output to the host.

0010-0010 Read Data Memory

Read D ata from Data Memory. This command requires four follow-on transfer cycles, two for the starting address

and two for the word read count, starting w ith the LSB address and ending with the MSB read count. The address is

moved to the ICDA register and the word read count is moved to the ICD D reg ister by the debug engine. This

information is directly accessible by the ROM code. At the completion of this command period, the debug engine

updates the CM D [3:0] b its to 0010b and perform s a jump to ROM code at 8010h. The ROM debug service routine

w il l load ICD B from data memory according to address and count infor mation provided by the host.

0010-0011 Read P rogram Stack

Read D ata from Program Stack. This com mand requires four follow -on transfer cycles, two for the starting address

and two for the read count, starting w ith the LSB address and ending w ith the MSB read count. The address is

moved to the ICDA register and the read count is moved to the ICD D regis ter by the debug engine. This infor mation

is di rectly accessib le by the ROM code. At the comp letion of this command period, the debug engine updates the

C MD[3:0] bits to 0011b and perform s a jump to ROM code at 8010h. The ROM Debug service routine w il l pop data

out from the stack according to the information received in the ICDA and ICDD reg ister. The stack pointer is p re-

decremented for each pop operation.

0010-0100 Write Register

Wri te Data to a Selected Register. This command requires four follow-on transfer cycles , two for the reg ister

address and two for the data, starting w ith the LSB address and ending with the M SB data. The address is moved to

the ICDA register and the data is moved to the ICD D reg ister by the debug engine. This infor mation

is di rectly accessib le by the ROM code. At the comp letion of this com m and per iod, the debug engine updates the

C MD[3:0] bits to 0100b and perform s a jump to ROM code at 8010h. The ROM Debug service routine w il l update

the select register according to the infor mation received in the ICDA and ICD D reg isters.

0010-0101 W r ite Data Memory

Wri te Data to a Selected Data Memory Locatio n. This com mand requires four follow-on transfer cycles , two for

the me mory add ress and two for the data, starting w ith the LSB address and ending w ith the MSB data. The addres s

is moved to the ICD A register and the data is moved to the ICD D register by the debug engine. This information is

di rectly acces sib le by the ROM code. At the completion of this command period, the debug engine updates the

C MD[3:0] bits to 0101b and perform s a jump to ROM code at 8010h. The ROM Debug service routine wi ll update

the selected data memory location according to the infor mation received in the |C DA and ICDD registers.

0010-0110 Trace

Trace Command. This command allows s ingle stepp ing the CP U and requires no follow-on transfer cycle. The

trace operation is a ‘debug mode exit, one cycle C PU execution, debug mode entry ’ s equence.

0010-0111 Return

Return Co mmand. This command ter m inates the debug mode and returns the debug engine to background mode.

This allows the CPU to resume its nor mal operation at the point where it has been last interrupted.

0010-1000 Unlock Password

U nlock the Passw ord Lock. This command requires 32 follow-on trans fer cycles each containing a byte value

to be compared w ith the progra m me mory pass word for the pur pose of clear ing the PWL bit and granting access to

protected debug and loader functions . When this command is received, the debug engine updates the C MD[3:0]

bits to 1000b and performs a jump to ROM code at 8010h. Data is loaded to the ICDB register when each byte of

data is received, beginning w ith the LSB of the least s ignificant word fir s t and end w ith the MSB of the most

si gnificant word.

0010-1001 Read Register

Read fr om a Selected Internal Register. This command requires two follow-on transfer cycles , starting with the

LSB address and ending w ith the MSB addres s. The address is moved to ICDA register by the debug engine. This

information is directly accessible by the ROM code. At the completion of this command period, the debug engine

updates the CM D [3:0] b its to 1001b and perform s a jump to ROM code at 8010h. The ROM Debug service routine

w il l always as sume a 16-bit register length and return the requested data LSB fi rst.

Internally, the ROM can ascertain when new data is available or when it can output the next data byte via the TXC flag. The TXC flag is an

important indicator between the debug engine and the utility ROM debug routines. The utility ROM firmware sets the TXC flag to 1 to indi-

cate that valid data has been loaded to the ICDB register. The debug engine clears the TXC flag to 0 to indicate completion of a data shift

cycle, thus allowing the ROM to continue execution of a requested task that is still in progress. The utility ROM signals that it has com-

pleted a requested task by setting the ROM operation done (ROD) bit of the SC register to logic 1. The ROD bit is reset by the debug

engine when it recognizes the done condition. Table 12-2 shows the debug mode commands supported by the MAXQ7667. Note that

background mode commands are supported inside debug mode. Encodings not listed in this table are not supported in debug mode and

are treated as no operations.

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